ROHS MC9S08QE128 Reference Manual page 331

18.3.3.10 Debug Comparator B Extension Register (DBGCBX)
Module Base + 0x0009
7
R
RWBEN
W
POR
or non- 0
end-run
Reset
U
1
end-run
= Unimplemented or Reserved
Figure 18-11. Debug Comparator B Extension Register (DBGCBX)
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Field
7 Read/Write Comparator B Enable Bit — The RWBEN bit controls whether read or write comparison is enabled
RWBEN for Comparator B. In full modes, RWAEN and RWA are used to control comparison of R/W and RWBEN is
ignored.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
6 Read/Write Comparator B Value Bit — The RWB bit controls whether read or write is used in compare for
RWB Comparator B. The RWB bit is not used if RWBEN = 0. In full modes, RWAEN and RWA are used to control
comparison of R/W and RWB is ignored.
0 Write cycle will be matched
1 Read cycle will be matched
5 Comparator B Page Select Bit — This PAGSEL bit controls whether Comparator B will be qualified with the
PAGSEL internal signal (mmu_papge_sel) that indicates an extended access through the PPAGE mechanism. When
mmu_ppage_sel = 1, the 17-bit core address is a paged program access, and the 17-bit core address is made
up of PPAGE[2:0]:addr[13:0]. When mmu_papge_sel = 0, the 17-bit core address is either a 16-bit CPU address
with a leading 0 in bit 16, or a 17-bit linear address pointer value. This bit is not used in full modes where
comparator B is used to match the data value.
0 Match qualified by mmu_ppage_sel = 0 so address bits [16:0] correspond to a 17-bit CPU address with a
leading zero at bit 16, or a 17-bit linear address pointer address
1 Match qualified by mmu_ppage_sel = 1 so address bits [16:0] compare to flash memory address made up of
PPAGE[2:0]:addr[13:0]
0 Comparator B Extended Address Bit 16 Compare Bit — The Comparator B bit 16 compare bit controls
Bit 16 whether Comparator B will compare the core address bus bit 16 to a logic 1 or logic 0. This bit is not used in full
modes where comparator B is used to match the data value.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Freescale Semiconductor
6 5
RWB PAGSEL
0 0
U U
Table 18-12. DBGCBX Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
0 0
0 0
0 0
Description
Chapter 18 Debug Module (DBG) (128K)
2 1
0 0
0 0
0 0
0
Bit 16
0
U
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