ROHS MC9S08QE128 Reference Manual page 16

Section Number
16.1.1 ACMP/TPM Configuration Information .........................................................................283
16.1.2 TPM Clock Gating ..........................................................................................................283
16.1.3 Interrupt Vector ...............................................................................................................283
16.1.4 Features ...........................................................................................................................285
16.1.5 Modes of Operation ........................................................................................................285
16.1.6 Block Diagram ................................................................................................................286
16.2 Signal Description .........................................................................................................................288
16.2.1 Detailed Signal Descriptions ...........................................................................................288
16.3 Register Definition ........................................................................................................................292
16.3.1 TPM Status and Control Register (TPMxSC) ................................................................292
16.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................293
16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................294
16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................295
16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................296
16.4 Functional Description ..................................................................................................................298
16.4.1 Counter ............................................................................................................................298
16.4.2 Channel Mode Selection .................................................................................................300
16.5 Reset Overview .............................................................................................................................303
16.5.1 General ............................................................................................................................303
16.5.2 Description of Reset Operation .......................................................................................303
16.6 Interrupts .......................................................................................................................................303
16.6.1 General ............................................................................................................................303
16.6.2 Description of Interrupt Operation ..................................................................................304
17.1 Introduction ...................................................................................................................................307
17.1.1 Forcing Active Background ............................................................................................307
17.1.2 DBG Clock Gating ..........................................................................................................307
17.1.3 Module Configuration .....................................................................................................307
17.1.4 Features ...........................................................................................................................308
17.2 Background Debug Controller (BDC) ..........................................................................................308
17.2.1 BKGD Pin Description ...................................................................................................309
17.2.2 Communication Details ..................................................................................................309
17.2.3 BDC Commands .............................................................................................................313
17.2.4 BDC Hardware Breakpoint .............................................................................................315
17.3 Register Definition ........................................................................................................................315
17.3.1 BDC Registers and Control Bits .....................................................................................316
17.3.2 System Background Debug Force Reset Register (SBDFR) ..........................................318
Freescale Semiconductor
Title
Chapter 17
Development Support
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Page
17