Bus Frequency Divider; Low Power Bit Usage; Dco Maximum Frequency With 32.768 Khz Oscillator; Internal Reference Clock - ROHS MC9S08QE128 Reference Manual

11.4.3

Bus Frequency Divider

The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur
immediately.
11.4.4

Low Power Bit Usage

The low power bit (LP) is provided to allow the FLL to be disabled and thus conserve power when it is not
being used. The DRS bits can not be written while LP bit is 1.
However, in some applications it may be desirable to allow the FLL to be enabled and to lock for maximum
accuracy before switching to an FLL engaged mode. Do this by writing the LP bit to 0.
11.4.5

DCO Maximum Frequency with 32.768 kHz Oscillator

The FLL has an option to change the clock multiplier for the selected DCO range such that it results in the
maximum bus frequency with a common 32.768 kHZ crystal reference clock.
11.4.6

Internal Reference Clock

When IRCLKEN is set the internal reference clock signal will be presented as ICSIRCLK, which can be
used as an additional clock source. The ICSIRCLK frequency can be re-targeted by trimming the period
of the internal reference clock. This can be done by writing a new value to the TRIM bits in the ICSTRM
register. Writing a larger value will slow down the ICSIRCLK frequency, and writing a smaller value to
the ICSTRM register will speed up the ICSIRCLK frequency. The TRIM bits will effect the ICSOUT
frequency if the ICS is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or FLL bypassed
internal low power (FBILP) mode.
Until ICSIRCLK is trimmed, programming low reference divider (RDIV) factors may result in ICSOUT
frequencies that exceed the maximum chip-level frequency and violate the chip-level clock timing
specifications (see the
If IREFSTEN is set and the IRCLKEN bit is written to 1, the internal reference clock will keep running
during stop mode in order to provide a fast recovery upon exiting stop.
All MCU devices are factory programmed with a trim value in a reserved memory location. This value is
uploaded to the ICSTRM register and ICS FTRIM register during any reset initialization. For finer
precision, the user can trim the internal oscillator in the application and set the FTRIM bit accordingly.
Freescale Semiconductor
Device Overview chapter).
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Internal Clock Source (S08ICSV3)
215