Compare Value High Register (Adccvh); Compare Value Low Register (Adccvl); Configuration Register (Adccfg) - ROHS MC9S08QE128 Reference Manual

7
R ADR7
W
Reset: 0
10.3.5

Compare Value High Register (ADCCVH)

In 12-bit mode, the ADCCVH register holds the upper four bits of the 12-bit compare value. These bits are
compared to the upper four bits of the result following a conversion in 12-bit mode when the compare
function is enabled.
7
R 0
W
Reset: 0
In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV9 –
ADCV8). These bits are compared to the upper two bits of the result following a conversion in 10-bit mode
when the compare function is enabled.
In 8-bit mode, ADCCVH is not used during compare.
10.3.6

Compare Value Low Register (ADCCVL)

This register holds the lower 8 bits of the 12-bit or 10-bit compare value, or all 8 bits of the 8-bit compare
value. Bits ADCV7:ADCV0 are compared to the lower 8 bits of the result following a conversion in 12-bit,
10-bit or 8-bit mode.
7
R
ADCV7
W
Reset: 0
10.3.7 Configuration Register (ADCCFG)
ADCCFG is used to select the mode of operation, clock source, clock divide, and configure for low power
or long sample time.
Freescale Semiconductor
6 5
ADR6 ADR5
0 0
= Unimplemented or Reserved
Figure 10-7. Data Result Low Register (ADCRL)
6 5
0 0
0 0
= Unimplemented or Reserved
Figure 10-8. Compare Value High Register (ADCCVH)
6 5
ADCV6 ADCV5
0 0
Figure 10-9. Compare Value Low Register(ADCCVL)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
12-bit Analog-to-Digital Converter (S08ADCV1)
4 3
ADR4 ADR3
0 0
4 3
0
ADCV11
0 0
4 3
ADCV4 ADCV3
0 0
2 1
ADR2 ADR1
0 0
2 1
ADCV10 ADCV9 ADCV8
0 0
2 1
ADCV2 ADCV1 ADCV0
0 0
0
ADR0
0
0
0
0
0
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