System Clock Gating Control 1 Register (Scgc1) - ROHS MC9S08QE128 Reference Manual

Field
5 Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (V
LVDV 0 Low trip point selected (V
1 High trip point selected (V
4 Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (V
LVWV 0 Low trip point selected (V
1 High trip point selected (V
3 Low-Voltage Warning Interrupt Enable — This bit enables hardware interrupt requests for LVWF.
LVWIE 0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVWF = 1.
LVDV:LVWV
1
See the data sheet for minimum and maximum values.
2
This setting is not recommended
5.8.10

System Clock Gating Control 1 Register (SCGC1)

This high page register contains control bits to enable or disable the bus clock to the TPMx, ADC, IICx,
and SCIx modules. Gating off the clocks to unused peripherals is used to reduce the MCU's run and wait
currents. See Section 5.7, "Peripheral Clock
User software should disable the peripheral before disabling the clocks to
the peripheral. When clocks are re-enabled to a peripheral, the peripheral
registers need to be re-initialized by user software.
7
R
TPM3
W
Reset: 1
Figure 5-12. System Clock Gating Control 1 Register (SCGC1)
Freescale Semiconductor
Table 5-12. SPMSC3 Register Field Descriptions (continued)
= V
LVD LVDL
= V
LVD LVDH
= V
LVW LVWL
= V
LVW LVWH
Table 5-13. LVD and LVW Trip Point Typical Values
LVW Trip Point
0:0 V
LVWL
0:1 V
LVWH
2
1:0 V
LVWL
1:1 V
LVWH
Gating," for more information.
6 5
TPM2 TPM1
1 1
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Chapter 5 Resets, Interrupts, and General System Control
Description
).
).
).
).
= 2.15 V
= 2.48 V
= 2.15 V
= 2.48 V
NOTE
4 3
ADC IIC2
1 1
).
LVD
LVW
1
LVD Trip Point
V = 1.84 V
LVDL
V = 2.15 V
LVDH
2 1
IIC1 SCI2
1 1
).
0
SCI1
1
107