Module Configurations - ROHS MC9S08QE128 Reference Manual

10.1.2 Module Configurations
This section provides device-specific information for configuring the ADC on the MC9S08QE128 Series.
10.1.2.1 Channel Assignments
The ADC channel assignments for the MC9S08QE128 Series devices are shown in
channels convert to an unknown value.
ADCH Channel
00000 AD0
00001 AD1
00010 AD2
00011 AD3
00100 AD4
00101 AD5
00110 AD6
00111 AD7
01000 AD8
01001 AD9
01010 AD10
01011 AD11
01100 AD12
01101 AD13
01110 AD14
01111 AD15
1
For information, see Section 10.1.2.4, "Temperature
Selecting the internal bandgap channel requires SPMSC1[BGBE] to be set,
see Section 5.8.7, "System Power Management Status and Control 1
Register (SPMSC1)."
data sheet.
10.1.2.2 Alternate Clock
The ADC is capable of performing conversions using the MCU bus clock, the bus clock divided by two,
the local asynchronous clock (ADACK) within the module, or the alternate clock (ALTCLK). The
ALTCLK on the MC9S08QE128 Series is the ICSERCLK. See
(S08ICSV3)," for more information.
Freescale Semiconductor
Table 10-1. ADC Channel Assignment
Input Pin Control
PTA0/ADP0 ADPC0
PTA1/ADP1 ADPC1
PTA2/ADP2 ADPC2
PTA3/ADP3 ADPC3
PTB0/ADP4 ADPC4
PTB1/ADP5 ADPC5
PTB2/ADP6 ADPC6
PTB3/ADP7 ADPC7
PTA6/ADP8 N/A
PTA7/ADP9 N/A
PTF0/ADP10 N/A
PTF1/ADP11 N/A
PTF2/ADP12 N/A
PTF3/ADP13 N/A
PTF4/ADP14 N/A
PTF5/ADP15 N/A
Sensor."
For the value of bandgap voltage reference see the
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
ADCH Channel
10000 AD16
10001 AD17
10010 AD18
10011 AD19
10100 AD20
10101 AD21
10110 AD22
10111 AD23
11000 AD24
11001 AD25
11010 AD26
11011 AD27
11100 —
11101 V
REFH
11110 V
REFL
11111 Module
Disabled
NOTE
Chapter 11, "Internal Clock Source
Table 10-1. Reserved
Input Pin Control
PTF6/ADP16 N/A
PTF7/ADP17 N/A
PTG2/ADP18 N/A
PTG3/ADP19 N/A
PTG4/ADP20 N/A
PTG5/ADP21 N/A
PTG6/ADP22 N/A
PTG7/ADP23 N/A
Reserved N/A
Reserved N/A
Temperature N/A
1
Sensor
Internal Bandgap N/A
Reserved N/A
V N/A
DD
V N/A
SS
None N/A
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