ROHS MC9S08QE128 Reference Manual page 164

Chapter 8 Central Processor Unit (S08CPUV4)
Bit-Manipulation Branch
00 5 10 5 20 3 30
BRSET0 BSET0 BRA NEG
3 DIR 2 DIR 2 REL 2
01 5 11 5 21 3 31
BRCLR0 BCLR0 BRN CBEQ
3 DIR 2 DIR 2 REL 3
02 5 12 5 22 3 32
BRSET1 BSET1 BHI LDHX
3 DIR 2 DIR 2 REL 3
03 5 13 5 23 3 33
BRCLR1 BCLR1 BLS COM
3 DIR 2 DIR 2 REL 2
04 5 14 5 24 3 34
BRSET2 BSET2 BCC LSR
3 DIR 2 DIR 2 REL 2
05 5 15 5 25 3 35
BRCLR2 BCLR2 BCS STHX
3 DIR 2 DIR 2 REL 2
06 5 16 5 26 3 36
BRSET3 BSET3 BNE ROR
3 DIR 2 DIR 2 REL 2
07 5 17 5 27 3 37
BRCLR3 BCLR3 BEQ ASR
3 DIR 2 DIR 2 REL 2
08 5 18 5 28 3 38
BRSET4 BSET4 BHCC LSL
3 DIR 2 DIR 2 REL 2
09 5 19 5 29 3 39
BRCLR4 BCLR4 BHCS ROL
3 DIR 2 DIR 2 REL 2
0A 5 1A 5 2A 3 3A
BRSET5 BSET5 BPL DEC
3 DIR 2 DIR 2 REL 2
0B 5 1B 5 2B 3 3B
BRCLR5 BCLR5 BMI DBNZ
3 DIR 2 DIR 2 REL 3
0C 5 1C 5 2C 3 3C
BRSET6 BSET6 BMC INC
3 DIR 2 DIR 2 REL 2
0D 5 1D 5 2D 3 3D
BRCLR6 BCLR6 BMS TST
3 DIR 2 DIR 2 REL 2
0E 5 1E 5 2E 3 3E
BRSET7 BSET7 BIL CPHX
3 DIR 2 DIR 2 REL 3
0F 5 1F 5 2F 3 3F
BRCLR7 BCLR7 BIH CLR
3 DIR 2 DIR 2 REL 2
INH Inherent REL Relative
IMM Immediate IX Indexed, No Offset
DIR Direct IX1 Indexed, 8-Bit Offset
EXT Extended IX2 Indexed, 16-Bit Offset
DD DIR to DIR IMD IMM to DIR
IX+D IX+ to DIR DIX+ DIR to IX+
164
Table 8-3. Opcode Map (Sheet 1 of 2)
Read-Modify-Write
5 40 1 50 1 60 5
NEGA NEGX NEG
DIR 1 INH 1 INH 2 IX1
5 41 4 51 4 61 5
CBEQA CBEQX CBEQ
DIR 3 IMM 3 IMM 3 IX1+
5 42 5 52 6 62 1
MUL DIV NSA
EXT 1 INH 1 INH 1 INH
5 43 1 53 1 63 5
COMA COMX COM
DIR 1 INH 1 INH 2 IX1
5 44 1 54 1 64 5
LSRA LSRX LSR
DIR 1 INH 1 INH 2 IX1
4 45 3 55 4 65 3
LDHX LDHX CPHX
DIR 3 IMM 2 DIR 3 IMM
5 46 1 56 1 66 5
RORA RORX ROR
DIR 1 INH 1 INH 2 IX1
5 47 1 57 1 67 5
ASRA ASRX ASR
DIR 1 INH 1 INH 2 IX1
5 48 1 58 1 68 5
LSLA LSLX LSL
DIR 1 INH 1 INH 2 IX1
5 49 1 59 1 69 5
ROLA ROLX ROL
DIR 1 INH 1 INH 2 IX1
5 4A 1 5A 1 6A 5
DECA DECX DEC
DIR 1 INH 1 INH 2 IX1
7 4B 4 5B 4 6B 7
DBNZA DBNZX DBNZ
DIR 2 INH 2 INH 3 IX1
5 4C 1 5C 1 6C 5
INCA INCX INC
DIR 1 INH 1 INH 2 IX1
4 4D 1 5D 1 6D 4
TSTA TSTX TST
DIR 1 INH 1 INH 2 IX1
6 4E 5 5E 5 6E 4
MOV MOV MOV
EXT 3 DD 2 DIX+ 3 IMD
5 4F 1 5F 1 6F 5
CLRA CLRX CLR
DIR 1 INH 1 INH 2 IX1
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Control
70 4 80 9 90 3 A0
NEG RTI BGE SUB
1 IX 1 INH 2 REL 2
71 5 81 6 91 3 A1
CBEQ RTS BLT CMP
2 IX+ 1 INH 2 REL 2
72 1 82 5+ 92 3 A2
DAA BGND BGT SBC
1 INH 1 INH 2 REL 2
73 4 83 11 93 3 A3
COM SWI BLE CPX
1 IX 1 INH 2 REL 2
74 4 84 1 94 2 A4
LSR TAP TXS AND
1 IX 1 INH 1 INH 2
75 5 85 1 95 2 A5
CPHX TPA TSX BIT
2 DIR 1 INH 1 INH 2
76 4 86 3 96 5 A6
ROR PULA STHX LDA
1 IX 1 INH 3 EXT 2
77 4 87 2 97 1 A7
ASR PSHA TAX AIS
1 IX 1 INH 1 INH 2
78 4 88 3 98 1 A8
LSL PULX CLC EOR
1 IX 1 INH 1 INH 2
79 4 89 2 99 1 A9
ROL PSHX SEC ADC
1 IX 1 INH 1 INH 2
7A 4 8A 3 9A 1 AA
DEC PULH CLI ORA
1 IX 1 INH 1 INH 2
7B 6 8B 2 9B 1 AB
DBNZ PSHH SEI ADD
2 IX 1 INH 1 INH 2
7C 4 8C 1 9C 1 AC
INC CLRH RSP CALL
1 IX 1 INH 1 INH 4
7D 3 8D 7 9D 1 AD
TST RTC NOP BSR
1 IX 1 INH 1 INH 2
7E 5 8E 2+ 9E AE
MOV STOP Page 2 LDX
2 IX+D 1 INH 2
7F 4 8F 2+ 9F 1 AF
CLR WAIT TXA AIX
1 IX 1 INH 1 INH 2
Register/Memory
2 B0 3 C0 4 D0
SUB SUB SUB
IMM 2 DIR 3 EXT 3 IX2
2 B1 3 C1 4 D1
CMP CMP CMP
IMM 2 DIR 3 EXT 3 IX2
2 B2 3 C2 4 D2
SBC SBC SBC
IMM 2 DIR 3 EXT 3 IX2
2 B3 3 C3 4 D3
CPX CPX CPX
IMM 2 DIR 3 EXT 3 IX2
2 B4 3 C4 4 D4
AND AND AND
IMM 2 DIR 3 EXT 3 IX2
2 B5 3 C5 4 D5
BIT BIT BIT
IMM 2 DIR 3 EXT 3 IX2
2 B6 3 C6 4 D6
LDA LDA LDA
IMM 2 DIR 3 EXT 3 IX2
2 B7 3 C7 4 D7
STA STA STA
IMM 2 DIR 3 EXT 3 IX2
2 B8 3 C8 4 D8
EOR EOR EOR
IMM 2 DIR 3 EXT 3 IX2
2 B9 3 C9 4 D9
ADC ADC ADC
IMM 2 DIR 3 EXT 3 IX2
2 BA 3 CA 4 DA
ORA ORA ORA
IMM 2 DIR 3 EXT 3 IX2
2 BB 3 CB 4 DB
ADD ADD ADD
IMM 2 DIR 3 EXT 3 IX2
8 BC 3 CC 4 DC
JMP JMP JMP
EXT 2 DIR 3 EXT 3 IX2
5 BD 5 CD 6 DD
JSR JSR JSR
REL 2 DIR 3 EXT 3 IX2
2 BE 3 CE 4 DE
LDX LDX LDX
IMM 2 DIR 3 EXT 3 IX2
2 BF 3 CF 4 DF
STX STX STX
IMM 2 DIR 3 EXT 3 IX2
Opcode in
F0 3 HCS08 Cycles
Hexadecimal
SUB Instruction Mnemonic
Addressing Mode
Number of Bytes 1 IX
Freescale Semiconductor
4 E0 3 F0 3
SUB SUB
2 IX1 1 IX
4 E1 3 F1 3
CMP CMP
2 IX1 1 IX
4 E2 3 F2 3
SBC SBC
2 IX1 1 IX
4 E3 3 F3 3
CPX CPX
2 IX1 1 IX
4 E4 3 F4 3
AND AND
2 IX1 1 IX
4 E5 3 F5 3
BIT BIT
2 IX1 1 IX
4 E6 3 F6 3
LDA LDA
2 IX1 1 IX
4 E7 3 F7 2
STA STA
2 IX1 1 IX
4 E8 3 F8 3
EOR EOR
2 IX1 1 IX
4 E9 3 F9 3
ADC ADC
2 IX1 1 IX
4 EA 3 FA 3
ORA ORA
2 IX1 1 IX
4 EB 3 FB 3
ADD ADD
2 IX1 1 IX
4 EC 3 FC 3
JMP JMP
2 IX1 1 IX
6 ED 5 FD 5
JSR JSR
2 IX1 1 IX
4 EE 3 FE 3
LDX LDX
2 IX1 1 IX
4 EF 3 FF 2
STX STX
2 IX1 1 IX