ROHS MC9S08QE128 Reference Manual page 132

Chapter 6 Parallel Input/Output Control
6.5.7.1 Port G Data Register (PTGD)
7
R
PTGD7
W
Reset: 0
Field
7:0 Port G Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port G
PTGD[7:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pull-ups disabled.
6.5.7.2 Port G Data Direction Register (PTGDD)
7
R
PTGDD7
W
Reset: 0
Field
7:0 Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGDD[7:0] PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.
6.5.7.3 Port G Pull Enable Register (PTGPE)
The port G enable register (PTGPE) enables pull-ups on the corresponding PTG pin. In some cases, a
pull-down device will be enabled if pull-downs are supported by an alternative pin function, such as KBI.
7
R
PTGPE7
W
Reset: 0
132
6 5
PTGD6 PTGD5
0 0
Figure 6-39. Port G Data Register (PTGD)
Table 6-37. PTGD Register Field Descriptions
6 5
PTGDD6 PTGDD5
0 0
Figure 6-40. Port G Data Direction Register (PTGDD)
Table 6-38. PTGDD Register Field Descriptions
6 5
PTGPE6 PTGPE5
0 0
Figure 6-41. Internal Pull Enable for Port G Register (PTGPE)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
PTGD4 PTGD3
0 0
Description
4 3
PTGDD4 PTGDD3
0 0
Description
4 3
PTGPE4 PTGPE3
0 0
2 1
PTGD2 PTGD1
0 0
2 1
PTGDD2 PTGDD1
0 0
2 1
PTGPE2 PTGPE1
0 0
Freescale Semiconductor
0
PTGD0
0
0
PTGDD0
0
0
PTGPE0
0