Register Addresses And Bit Assignments - ROHS MC9S08QE128 Reference Manual

4.3

Register Addresses and Bit Assignments

The registers in the MC9S08QE128 Series are divided into these groups:
• Direct-page registers are located in the first 128 locations in the memory map; these are accessible
with efficient direct addressing mode instructions.
• High-page registers are used much less often, so they are located above 0x1800 in the memory
map. This leaves more room in the direct page for more frequently used registers and RAM.
• The nonvolatile register area consists of a block of 16 locations in flash memory at
0xFFB0–0xFFBF. Nonvolatile register locations include:
— NVPROT and NVOPT are loaded into working registers at reset
— An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to
secure memory
Because the nonvolatile register locations are flash memory, they must be erased and programmed
like other flash memory locations.
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation
instructions can be used to access any bit in any direct-page register.
user-accessible direct-page registers and control bits.
The direct page registers in
only the lower byte of the address. Because of this, the lower byte of the address in column one is shown
in bold text. In Table 4-3
Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart from the
bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0
indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit
locations that could read as 1s or 0s. When writing to these bits, write a 0 unless otherwise specified.
Freescale Semiconductor
Table 4-2 can use the more efficient direct addressing mode, which requires
and Table 4-4, the whole address in column one is shown in bold. In
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Chapter 4 Memory
Table 4-2
is a summary of all
Table 4-2,
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