Low-Voltage Detect (Lvd) System; Power-On Reset Operation; Low-Voltage Detection (Lvd) Reset Operation; Low-Voltage Detection (Lvd) Interrupt Operation - ROHS MC9S08QE128 Reference Manual

Chapter 5 Resets, Interrupts, and General System Control
5.6

Low-Voltage Detect (LVD) System

The MC9S08QE128 Series includes a system to protect against low voltage conditions to protect memory
contents and control MCU system states during supply voltage variations. The system is comprised of a
power-on reset (POR) circuit and a LVD circuit with a user selectable trip voltage, either high (V
low (V ). The LVD circuit is enabled when LVDE in SPMSC1 is set and the trip voltage is selected
LVDL
by LVDV in SPMSC3. The LVD is disabled upon entering either of the stop modes unless LVDSE is set
in SPMSC1. If LVDSE and LVDE are both set, then the MCU will enter stop3 instead of stop2, and the
current consumption in stop3 with the LVD enabled will be greater.
5.6.1

Power-On Reset Operation

When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset
rearm voltage level, V
POR
LVD circuit will hold the MCU in reset until the supply has risen above the low voltage detection low
threshold, V . Both the POR bit and the LVD bit in SRS are set following a POR.
LVDL
5.6.2

Low-Voltage Detection (LVD) Reset Operation

The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. The low voltage detection threshold is determined by the LVDV bit. After an LVD reset has
occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the low
voltage detection threshold. The LVD bit in the SRS register is set following either an LVD reset or POR.
5.6.3

Low-Voltage Detection (LVD) Interrupt Operation

When a low voltage condition is detected and the LVD circuit is configured using SPMSC1 for interrupt
operation (LVDE set, LVDIE set, and LVDRE clear), then LVDF in SPMSC1 will be set and an LVD
interrupt request will occur. The LVDF bit is cleared by writing a 1 to the LVDACK bit in SPMSC1.
5.6.4

Low-Voltage Warning (LVW) Interrupt Operation

The LVD system has a low voltage warning flag (LVWF) to indicate to the user that the supply voltage is
approaching, but is above, the LVD voltage. The LVW also has an interrupt associated with it, enabled by
setting the LVWIE bit in the SPMSC3 register. If enabled, an LVW interrupt request will occur when the
LVWF is set. LVWF is cleared by writing a 1 to the LVWACK bit in SPMSC3. There are two user
selectable trip voltages for the LVW, one high (V
by LVWV in SPMSC3.
5.7

Peripheral Clock Gating

The MC9S08QE128 Series includes a clock gating system to manage the bus clock sources to the
individual peripherals. Using this system, the user can enable or disable the bus clock to each of the
peripherals at the clock source, eliminating unnecessary clocks to peripherals which are not in use and
thereby reducing the overall run and wait mode currents.
96
, the POR circuit will cause a reset condition. As the supply voltage rises, the
LVWH
MC9S08QE128 MCU Series Reference Manual, Rev. 2
) and one low (V ). The trip voltage is selected
LVWL
) or
LVDH
Freescale Semiconductor