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Chapter 4

Memory

4.1
MC9S08QE128 Series Memory Map
As shown in
Figure
4-1,
MCUs consists of RAM, flash program memory for nonvolatile data storage, and I/O and control/status
registers. The registers are divided into three groups:
Direct-page registers (0x0000 through 0x007F)
High-page registers (0x1800 through 0x187F)
Nonvolatile registers (0xFFB0 through 0xFFBF)
Extended Address
0x00000
When PPAGE 0 is
accessed through the
linear address pointer
or through the paging
window, the flash
memory is read.
0x03FFF
In the Figure 4-1,
BLUE arrows (for Program
and Constants), does NOT
depend on PPAGE; only
on: Logical 16 bit
address being OUT of
PAGE 2 range. Physical
A16 will always be "0".
PPAGES values 0, 1 & 3
ARE NOT OF ANY USE!!
This is why ISRs MUST
be located in pages 0,
1 or 3: they do NOT
use PPAGE, that is NOT
preserved over Inter-
rupts. NEVER locate
ISRs in page 2.
Inside ISRs you may
use code located on
Banked Memory (Pages
2,4,5,6,7) employing
CALL/RTC to save
and restore PPAGE.
Completly modifyied, corrected, commented and augmented by Luis G. Uribe C. Mar/Jun 2012
Freescale Semiconductor
Figure
4-2, and
Figure
DIRECT PAGE
PPAGE=0
REGISTERS
128 BYTES
RAM
6016 BYTES
HIGH
PAGE REGISTERS
FLASH
128 BYTES
16384 BYTES
RAM
2048 BYTES
FLASH
8064 BYTES
0x04000
PPAGE=1
FLASH
16384 BYTES
0x07FFF
0x08000
Paging Window -
Extended address-
es formed with
PPAGE and
A13:A0 of CPU ad-
dress
0x0BFFF
0x0C000
PPAGE=3
FLASH
16384 BYTES
0x0FFFF
Figure 4-1. MC9S08QE128 Memory Map
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4-3, on-chip memory in the MC9S08QE128 Series of
CPU Address
0x0000
0x007F
--0xFF: 128 Bytes Direct "Page" RAM,
0x0080
(not in the sense of MMU 8 Pages...)
0x17FF
When the CPU
accesses PPAGE 0
0x1800
directly, RAM and
registers, when present,
take priority over flash
0x187F
memory.
0x1880
0x207F
0x2080
0x3FFF
0x4000
PPAGE=2
PPAGE=1
0x7FFF
0x8000
PPAGE=0
FLASH
16384 BYTES
0xBFFF
0xC000
0xFFFF
PPAGE=7
PPAGE=6
PPAGE=5
PPAGE=4
PPAGE=3
flash
16384 BYTES
+64K:
up to
128K
RED arrows (program
and constants)
DOES DEPEND, indeed,
on both: PPAGE, and
Logical 16 bit add-
ress being INSIDE of
PAGE 2 range. If so,
Physical Address is:
PPAGE(2:0);A13:A0
A15:A14
are
used to form Physical
Address
NEVER
51

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