Data Result High Register (Adcrh); Data Result Low Register (Adcrl) - ROHS MC9S08QE128 Reference Manual

12-bit Analog-to-Digital Converter (S08ADCV1)
Field
5 Compare Function Enable — ACFE is used to enable the compare function.
ACFE 0 Compare function disabled
1 Compare function enabled
4 Compare Function Greater Than Enable — ACFGT is used to configure the compare function to trigger when
ACFGT the result of the conversion of the input being monitored is greater than or equal to the compare value. The
compare function defaults to triggering when the result of the compare of the input being monitored is less than
the compare value.
0 Compare triggers when input is less than compare level
1 Compare triggers when input is greater than or equal to compare level
10.3.3

Data Result High Register (ADCRH)

In 12-bit operation, ADCRH contains the upper four bits of the result of a 12-bit conversion.
7
R 0
W
Reset: 0
In 10-bit mode, ADCRH contains the upper two bits of the result of a 10-bit conversion. When configured
for 10-bit mode, ADR11 – ADR10 are equal to zero. When configured for 8-bit mode, ADR11 – ADR8
are equal to zero.
In both 12-bit and 10-bit mode, ADCRH is updated each time a conversion completes except when
automatic compare is enabled and the compare condition is not met. In 12-bit and 10-bit mode, reading
ADCRH prevents the ADC from transferring subsequent conversion results into the result registers until
ADCRL is read. If ADCRL is not read until after the next conversion is completed, then the intermediate
conversion result is lost. In 8-bit mode there is no interlocking with ADCRL.
In the case that the MODE bits are changed, any data in ADCRH becomes invalid.
10.3.4

Data Result Low Register (ADCRL)

ADCRL contains the lower eight bits of the result of a 12-bit or 10-bit conversion, and all eight bits of an
8-bit conversion. This register is updated each time a conversion completes except when automatic
compare is enabled and the compare condition is not met. In 12-bit and 10-bit mode, reading ADCRH
prevents the ADC from transferring subsequent conversion results into the result registers until ADCRL is
read. If ADCRL is not read until the after next conversion is completed, then the intermediate conversion
results will be lost. In 8-bit mode, there is no interlocking with ADCRH. In the case that the MODE bits
are changed, any data in ADCRL becomes invalid.
184
Table 10-4. ADCSC2 Register Field Descriptions (continued)
6 5
0 0
0 0
= Unimplemented or Reserved
Figure 10-6. Data Result High Register (ADCRH)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
4 3
0 ADR11 ADR10
0 0
2 1 0
ADR9 ADR8
0 0 0
Freescale Semiconductor