Sci Data Register (Scixd); Functional Description; Baud Rate Generation - ROHS MC9S08QE128 Reference Manual

Serial Communications Interface (S08SCIV4)
Field
4 Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output.
1
TXINV 0 Transmit data not inverted
1 Transmit data inverted
3 Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests.
ORIE 0 OR interrupts disabled (use polling).
1 Hardware interrupt requested when OR = 1.
2 Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests.
NEIE 0 NF interrupts disabled (use polling).
1 Hardware interrupt requested when NF = 1.
1 Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt
FEIE requests.
0 FE interrupts disabled (use polling).
1 Hardware interrupt requested when FE = 1.
0 Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt
PEIE requests.
0 PF interrupts disabled (use polling).
1 Hardware interrupt requested when PF = 1.
1
Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.
14.2.7

SCI Data Register (SCIxD)

This register is actually two separate registers. Reads return the contents of the read-only receive data
buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also
involved in the automatic flag clearing mechanisms for the SCI status flags.
7
R R7
W T7
Reset 0
14.3

Functional Description

The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote
devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block.
The transmitter and receiver operate independently, although they use the same baud rate generator. During
normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes
received data. The following describes each of the blocks of the SCI.
14.3.1

Baud Rate Generation

As shown in Figure 14-13, the clock source for the SCI baud rate generator is the bus-rate clock.
260
Table 14-7. SCIxC3 Field Descriptions (continued)
6 5
R6 R5
T6 T5
0 0
Figure 14-12. SCI Data Register (SCIxD)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
4 3
R4 R3
T4 T3
0 0
2 1
R2 R1
T2 T1
0 0
Freescale Semiconductor
0
R0
T0
0