ROHS MC9S08QE128 Reference Manual page 46

7
RUN
6
WAIT
Figure 3-1. Allowable Power Mode Transitions for the MC9S08QE128 Series
Figure 3-1 illustrates mode state transitions allowed between the legal states shown in
PTA5/IRQ/TPM1CLK/RESET must be asserted low (or an RTC interrupt must occur) in order to exit
stop2. Interrupts suffice for the other stop and wait modes.
Table 3-3 defines triggers for the various state transitions shown in
Transition #
1
2
3
4
Freescale Semiconductor
STOP3
1
2
STOP2
3
5
LPWAIT
Table 3-3. Triggers for Transitions Shown in
From
RUN LPRUN
LPRUN RUN
RUN STOP2
STOP2 RUN
LPRUN LPWAIT
LPWAIT LPRUN
LPRUN STOP3
STOP3 LPRUN
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4
LPRUN
Figure
Figure
To
Configure settings shown in
LPR=1 last
Clear LPR
Interrupt when LPWUI=1
Pre-configure settings shown in
STOP instruction
Assert zero on PTA5/IRQ/TPM1CLK/RESET
reload environment from RAM
WAIT instruction
Interrupt when LPWUI=0
STOP instruction
Interrupt when LPWUI=0
Chapter 3 Modes of Operation
Mode Regulator State
RUN Full on
WAIT Full on
LPRUN Standby
LPWAIT Standby
STOP3 Standby
STOP2 Partial power off
Table 3-1.
3-1.
3-1.
Trigger
Table 3-1, switch
Table 3-1, issue
1
,
47