Ics Control Register 2 (Icsc2); Ics Trim Register (Icstrm) - ROHS MC9S08QE128 Reference Manual

11.3.2

ICS Control Register 2 (ICSC2)

7
R
BDIV
W
Reset: 0
Field
7:6 Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits. This
BDIV controls the bus frequency.
00 Encoding 0 — Divides selected clock by 1
01 Encoding 1 — Divides selected clock by 2 (reset default)
10 Encoding 2 — Divides selected clock by 4
11 Encoding 3 — Divides selected clock by 8
5 Frequency Range Select — Selects the frequency range for the external oscillator.
RANGE 1 High frequency range selected for the external oscillator
0 Low frequency range selected for the external oscillator
4 High Gain Oscillator Select — The HGO bit controls the external oscillator mode of operation.
HGO 1 Configure external oscillator for high gain operation
0 Configure external oscillator for low power operation
3 Low Power Select — The LP bit controls whether the FLL is disabled in FLL bypassed modes.
LP 1 FLL is disabled in bypass modes unless BDM is active
0 FLL is not disabled in bypass mode
2 External Reference Select — The EREFS bit selects the source for the external reference clock.
EREFS 1 Oscillator requested
0 External Clock Source requested
1 External Reference Enable — The ERCLKEN bit enables the external reference clock for use as ICSERCLK.
ERCLKEN 1 ICSERCLK active
0 ICSERCLK inactive
0 External Reference Stop Enable — The EREFSTEN bit controls whether or not the external reference clock
EREFSTEN remains enabled when the ICS enters stop mode.
1 External reference clock stays enabled in stop if ERCLKEN is set before entering stop
0 External reference clock is disabled in stop
11.3.3

ICS Trim Register (ICSTRM)

7
R
W
Reset: Note: TRIM is loaded during reset from a factory programmed location when not in BDM mode. If in a BDM
mode, a default value of 0x80 is loaded.
Freescale Semiconductor
6 5
RANGE
1 0
Figure 11-4. ICS Control Register 2 (ICSC2)
Table 11-4. ICS Control Register 2 Field Descriptions
6 5
Figure 11-5. ICS Trim Register (ICSTRM)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
HGO LP EREFS
0 0
Description
4 3
TRIM
Internal Clock Source (S08ICSV3)
2 1 0
ERCLKEN EREFSTEN
0 0 0
2 1 0
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