ROHS MC9S08QE128 Reference Manual page 327

1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Field
Bits 7–0 Comparator B Low Compare Bits — The Comparator B Low compare bits control whether Comparator B will
compare the address bus or data bus bits [7:0] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0, compares to data if in Full mode
1 Compare corresponding address bit to a logic 1, compares to data if in Full mode
18.3.3.5 Debug Comparator C High Register (DBGCCH)
Module Base + 0x0004
7
R
Bit 15
W
POR
or non- 0
end-run
Reset
U
1
end-run
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Field
Bits 15–8 Comparator C High Compare Bits — The Comparator C High compare bits control whether Comparator C will
compare the address bus bits [15:8] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Freescale Semiconductor
Table 18-6. DBGCBL Field Descriptions
6 5
Bit 14 Bit 13
0 0
U U
Figure 18-6. Debug Comparator C High Register (DBGCCH)
Table 18-7. DBGCCH Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
4 3
Bit 12 Bit 11
0 0
U U
Description
Chapter 18 Debug Module (DBG) (128K)
2 1
Bit 10 Bit 9
0 0
U U
0
Bit 8
0
U
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