Ics Control Register 1 (Icsc1) - ROHS MC9S08QE128 Reference Manual

Internal Clock Source (S08ICSV3)
11.3.1

ICS Control Register 1 (ICSC1)

7
R
CLKS
W
Reset: 0
Field
7:6 Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency
CLKS depends on the value of the BDIV bits.
00 Output of FLL is selected.
01 Internal reference clock is selected.
10 External reference clock is selected.
11 Reserved, defaults to 00.
5:3 Reference Divider — Selects the amount to divide down the external reference clock. Resulting frequency must
RDIV be in the range 31.25 kHz to 39.0625 kHz. See
2 Internal Reference Select — The IREFS bit selects the reference clock source for the FLL.
IREFS 1 Internal reference clock selected
0 External reference clock selected
1 Internal Reference Clock Enable — The IRCLKEN bit enables the internal reference clock for use as
IRCLKEN ICSIRCLK.
1 ICSIRCLK active
0 ICSIRCLK inactive
0 Internal Reference Stop Enable — The IREFSTEN bit controls whether or not the internal reference clock
IREFSTEN remains enabled when the ICS enters stop mode.
1 Internal reference clock stays enabled in stop if IRCLKEN is set before entering stop
0 Internal reference clock is disabled in stop
208
6 5
0 0
Figure 11-3. ICS Control Register 1 (ICSC1)
Table 11-2. ICS Control Register 1 Field Descriptions
Table 11-3. Reference Divide Factor
RDIV RANGE=0
0
1
2
3
4
5
6
7 128
1
Reset default
MC9S08QE128 MCU Series Reference Manual, Rev. 1.11
4 3
RDIV
0 0
Description
Table 11-3 for the divide-by factors.
RANGE=1
1
32
1
2 64
4 128
8 256
16 512
32 1024
64 Reserved
Reserved
2 1
IREFS IRCLKEN IREFSTEN
1 0
Freescale Semiconductor
0
0