ROHS MC9S08QE128 Reference Manual page 186

12-bit Analog-to-Digital Converter (S08ADCV1)
7
R
ADLPC
W
Reset: 0
Field
7 Low Power Configuration — ADLPC controls the speed and power configuration of the successive
ADLPC approximation converter. This is used to optimize power consumption when higher sample rates are not required.
0 High speed configuration
1 Low power configuration: {FC31}The power is reduced at the expense of maximum clock speed.
6:5 Clock Divide Select — ADIV select the divide ratio used by the ADC to generate the internal clock ADCK.
ADIV Table 10-6 shows the available clock configurations.
4 Long Sample Time Configuration — ADLSMP selects between long and short sample time. This adjusts the
ADLSMP sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for
lower impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
0 Short sample time
1 Long sample time
3:2 Conversion Mode Selection — MODE bits are used to select between 12-, 10- or 8-bit operation. See
MODE Table 10-7.
1:0 Input Clock Select — ADICLK bits select the input clock source to generate the internal clock ADCK. See
ADICLK Table 10-8.
186
6 5
ADIV
0 0
Figure 10-10. Configuration Register (ADCCFG)
Table 10-5. ADCCFG Register Field Descriptions
Table 10-6. Clock Divide Select
ADIV Divide Ratio
00
01
10
11
Table 10-7. Conversion Modes
MODE
00 8-bit conversion (N=8)
01 12-bit conversion (N=12)
10 10-bit conversion (N=10)
11 Reserved
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
ADLSMP MODE
0 0
Description
1
Input clock ÷ 2
2
Input clock ÷ 4
4
Input clock ÷ 8
8
Mode Description
2 1
ADICLK
0 0
Clock Rate
Input clock
Freescale Semiconductor
0
0