Watchdog Counter (Wcn); External Chip-Select Signals And Wait-State Logic - Motorola MC68302 User Manual

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3.5.3.3 WATCHDOG COUNTER (WCN).
WCN is a 16-bit up-counter, appears as a
memory-mapped register, and may be read at any time. Clearing EN causes
the counter to be reset and disables the count operation.
A read cycle to WCN causes the current value of the timer to be read. When
working in MC68008 mode (BUSW is low), reading the high byte of WCN
will latch the low byte into a temporary register. When reading the low byte,
the temporary register value is read. Reading the timer does not affect the
counting operation.
A write cycle to WCN causes the counter and prescaler to be reset. In the
MC68008 mode (BUSW is low), a write cycle to either the high or low byte
resets the counter and the prescaler. A write cycle should be executed on a
regular basis so that the watchdog timer is never allowed to reach the ref-
erence value during normal program operation.
3.6 EXTERNAL CHIP-SELECT SIGNALS AND WAIT-STATE LOGIC
3-40
The MC68302 provides a set of four programmable chip-select signals. Each
chip-select signal has an identical in.ternal structure. For each memory area,
the user may also define an internally generated cycle termination signal
(DTACK). This feature eliminates board space that would be necessary for
cycle termination logic. The four chip-select signals allow four different classes
of memory to be used: e.g., high-speed static RAM, slower dynamic RAM,
EPROM, and nonvolatile RAM.
The chip-select block diagram is shown in Figure 3-6.
The chip-select logic is active for memory cycles generated by internal bus
masters (M68000 core, IDMA, SOMA), or external bus masters. These signals
are driven externally on the falling edge of AS and are valid shortly after AS
goes low.
The user should not program more than one chip-select line to the same
area. When this error occurs, the address compare logic will set address
decode conflict (ADC) in the system control register (SCR) and generate BERR
if address decode conflict enable (ADCE) is set. Only one chip-select line will
be driven because of internal line priorities. CSO has the highest priority, and
CS3 the lowest.
MC68302 USER'S MANUAL
MOTOROLA

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