I 2 C Bus Clock Control Register 0 (Iccr0) - Fujitsu MB90335 Series Hardware Manual

MB90335 Series
2
19.2.3 I C Bus Clock Control Register 0 (ICCR0)
The configuration and functions of I
described.
2
■ I
C Bus Clock Control Register 0 (ICCR0)
Figure 19.2-7 shows the bit configuration of I
Figure 19.2-7 Bit Configuration of I
ch.0:000072
R/W : Readable/writable
- : Undefined
X : Undefined value
The functions of I
[bit7, bit6] Undefinition bits
The read value is irregular. Nothing is affected when it is written.
[bit5] EN: ENable
It is an operation permission bit in the I
0
1
• When "0", each bit of IBSR0 register and IBCR0 register (except BER and BEIE bits) is cleared.
• Is cleared when BER bit is set.
[bit4 to bit0] CS4 to CS0:Clock Period Select 4-0
It is the bit which sets the serial clock frequency. The frequency fsck in the shift clock is set as shown in
the next formula.
Note:
The cycle + 4 is minimum overhead for checking that the output level of SCL0 pin has changed. If
delay is longer on the rising edge of SCL0 pin, or a slave device delays a clock, it exceeds this
value. Note that the frequency of the serial clock must be set to 100 kHz or less.
m and n for CS4 to CS0 is as shown in Table 19.2-1.
CM44-10137-6E
2
C bus clock control register 0 (ICCR0) are
bit 7 6 5 4
H
EN CS4 CS3 CS2 CS1 CS0
R/W R/W R/W R/W R/W R/W
2
C bus clock control registers 0 (ICCR0) are described below.
Operation disabled
Operation enabled
fsck
FUJITSU MICROELECTRONICS LIMITED
2
C bus clock control registers 0 (ICCR0).
2
C Bus Clock Control Register 0 (ICCR0)
3 2 1 0
ICCR0
2
I C bus clock control register 0
Initial value
2
C interface.
φ
φ
: Machine clock
m n
4
2
CHAPTER 19 I C INTERFACE
2
19.2 I C Interface Register
XX0XXXXX
B
443