Block Diagram Of Uart - Fujitsu MB90335 Series Hardware Manual

CHAPTER 18 UART

18.2 Block Diagram of UART

18.2 Block Diagram of UART
UART is composed of the following block.
■ Block Diagram of UART
Dedicated baud
rate gene rator
UART prescaler
control register
(UTCR0, UTCR1)
UART prescaler
reload register
(UTRLR0, UTRLR1)
Pin
SCK0, SCK1
External clock
Pin
SIN0, SIN1
Receive state
judge circuit
SMR0,
SMR1
register
388
Figure 18.2-1 Block Diagram of UART
Control bus
Receive
Receive clock
control
circuit
Start bit
detection circuit
Receive bit
counter
Receive parity
counter
Receiving
shift register
Receiving
end
SIDR0, SIDR1
2
F MC - 16LX Bus
MD1
MD0
SCKL
SCR0,
M2L2
SCR1
M2L1
register
M2L0
SCKE
SOE
FUJITSU MICROELECTRONICS LIMITED
Transfer clock
Transmit
control
circuit
Transmit start
circuit
Transmit bit
counter
Transmit parity
counter
Transmit
shift register
SODR0, SODR1
PEN
P
SBL
SSR0,
CL
SSR1
A/D
register
REC
RXE
TXE
MB90335 Series
Receive
interrupt signal
Transmit
interrupt signal
Pin
SOT0, SOT1
Transmission
end
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
CM44-10137-6E