Rcc Ahb3 Peripheral Reset Register (Rcc_Ahb3Rstr) - ST STM32F413 Reference Manual

Reset and clock control (RCC) for STM32F413/423
6.3.8

RCC AHB3 peripheral reset register (RCC_AHB3RSTR)

Address offset: 0x18
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 QSPIRST: QUADSPI module reset
Set and cleared by software.
0: does not reset QUADSPI module
1: resets QUADSPI module
Bit 0 FSMCRST: Flexible memory controller module reset
Set and cleared by software.
0: does not reset the FSMC module
1: resets the FSMC module
6.3.9 RCC APB1 peripheral reset register for (RCC_APB1RSTR)
Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
UART8 UART7 DAC PWR
RST RST RST RST
rw rw rw
15 14 13
SPI3 SPI2
Res. Res.
RST RST
rw rw
140/1284
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
28 27 26 25
CAN3 CAN2 CAN1
RST RST RST
rw rw rw rw
12 11 10 9
WWDG LPTIMER1
Res.
RST RST
rw rw
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
24 23 22
I2C4 I2C3 I2C2
RST RST RST
rw rw rw
8 7 6
TIM14 TIM13 TIM12
RST RST RST
rw rw rw
DocID029473 Rev 3
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. Res.
21 20 19
I2C1 UART5 UART4 USART3
RST RST RST
rw rw rw
5 4 3
TIM7 TIM6 TIM5
RST RST RST
rw rw rw
RM0430
17 16
Res. Res.
1 0
FSMC
QSPIRST
RST
rw rw
18 17 16
USART2
Res.
RST RST
rw rw
2 1 0
TIM4 TIM3 TIM2
RST RST RST
rw rw rw