Rcc Pll Configuration Register (Rcc_Pllcfgr) - ST STM32F413 Reference Manual

RM0430
6.3.2

RCC PLL configuration register (RCC_PLLCFGR)

Address offset: 0x04
Reset value: 0x2400 3010
Access: no wait state, word, half-word and byte access.
This register is used to configure the PLL clock outputs according to the formulas:
•
f
(VCO clock)
•
f
(PLL general clock output)
•
f
(USB OTG FS, SDIO, RNG clock output)
• f(
I2S, DFSDM clock output
31 30 29 28
Res. PLLR[2:0]
rw rw rw
15 14 13 12
Res.
rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:28 PLLR[2:0]: Main PLL (PLL) division factor for I2S, DFSDM clocks
Bits 27:24 PLLQ[3:0]: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number
generator clocks.
Caution: The USB OTG FS requires a 48 MHz clock to work correctly. The SDIO and the
Bit 23 Reserved, must be kept at reset value.
= f
(PLL clock input)
= f
(VCO clock)
) = f
27 26 25
PLLQ[3:0]
rw rw rw
11 10 9
PLLN[8:0]
rw rw rw
Set and cleared by software to control the frequency of the clock. These bits should be
written only if PLL is disabled.
Clock frequency = VCO frequency / PLLR with 2 ≤ PLLR ≤ 7
000: PLLR = 0, wrong configuration
001: PLLR = 1, wrong configuration
010: PLLR = 2
011: PLLR = 3
...
111: PLLR = 7
Set and cleared by software to control the frequency of USB OTG FS clock, the random
number generator clock and the SDIO clock. These bits should be written only if PLL is
disabled.
random number generator need a frequency lower than or equal to 48 MHz to work
correctly.
USB OTG FS clock frequency = VCO frequency / PLLQ with 2 ≤ PLLQ ≤ 15
0000: PLLQ = 0, wrong configuration
0001: PLLQ = 1, wrong configuration
0010: PLLQ = 2
0011: PLLQ = 3
0100: PLLQ = 4
...
1111: PLLQ = 15
Reset and clock control (RCC) for STM32F413/423
× (PLLN / PLLM)
/ PLLP
= f
(VCO clock)
/ PLLR
(VCO clock)
24 23 22
Res. PLLSRC
rw rw
8 7 6
rw rw rw
DocID029473 Rev 3
/ PLLQ
21 20 19
Res. Res. Res. Res.
5 4 3
PLLM[5:0]
rw rw rw
18 17 16
PLLP[1:0]
rw rw
2 1 0
rw rw rw
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