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21.5.3
SDRAM Interface AC characteristics
(Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V, CL = 150 pF)
Item
SDCLK[3:0] Cycle Time
SDCLK[3:0] High Time
SDCLK[3:0] Low Time
SDCLKIN Input Skew
ADDR[19:5] Output Delay
SDCS[3:0] * Output Delay
RAS * Output Delay
CAS * Output Delay
WE * Output Delay
CKE Output Delay
DQM[7:0] Output Delay
DATA[63:0] Output Delay (H → L, L → H)
DATA[63:0] Output Delay (Valid → Hi-
Z)
DATA[63:0] Output Delay (Valid → Hi-Z) t
DATA[63:0] Input Setup Time
DATA[63:0] Input Hold Time
DATA[63:0] Input Setup Time
DATA[63:0] Input Hold Time
*1) Becomes a 2-cycle signal when tDACT of SDCTR1 is "1".
*2) Becomes a 2-cycle signal when tSWB of SDCTR1 is "1".
*3) 2-cycle signal
For information on 2-cycle operation, see the description in Chapter 9 SDRAM Controller.
*4) The MAX value is is t
SDCLK[n]
OUTPUT
INPUT
Figure 21.5.3 Timing Diagram: Output Signal and Input Signal when in the Bypass Mode
Symbol
t
C
=50 pF, 16 mA buffer time
CYC_SDCLK
L
t
C
=50 pF, 16 mA buffer time
HIGH_SDCLK
L
t
C
=50 pF, 16 mA buffer time
LOW_SDCLK
L
When in the Non-bypass mode
t
BP
* 4)
C
=150 pF, 16 mA buffer, * 1)
L
t
VAL_ADDR1
C
= 80 pF, 16 mA buffer, * 1)
L
t
C
= 80 pF, 16 mA buffer
VAL_SDCS
L
C
=150 pF, 16 mA buffer, * 1)
L
t
VAL_RAS
C
= 80 pF, 16 mA buffer, * 1)
L
C
=150 pF, 16 mA buffer, * 3)
L
t
VAL_CAS
C
= 80 pF, 16 mA buffer, * 3)
L
C
=150 pF, 16 mA buffer, * 3)
L
t
VAL_WE
C
= 80 pF, 16 mA buffer, * 3)
L
C
=150 pF, 16 mA buffer
L
t
VAL_CKE
C
= 80 pF, 16 mA buffer
L
C
= 50 pF, 16 mA buffer, * 2)
L
t
VAL_DQM
C
= 30 pF, 16 mA buffer, * 2)
L
C
= 50 pF, 16 mA buffer, * 2)
L
t
VAL_DATA1
C
= 30 pF, 16 mA buffer, * 2)
L
C
= 50 pF, 16 mA buffer, * 2)
L
t
VAL_DATA1ZV
C
= 30 pF, 16 mA buffer, * 2)
L
C
= 50 pF, 16 mA buffer, * 2)
L
VAL_DATA1VZ
C
= 30 pF, 16 mA buffer, * 2)
L
t
When in the Bypass mode
SU_DATA1B
t
When in the Bypass mode
HO_DATA1B
t
When in the Non-bypass mode
SU_DATA1NB
t
When in the Non bypass mode
HO_DATA1NB
– 5.5 ns.
CYC_SDCLK
t
t
SU_*
inputs valid
(SDCLK Reference)
21-6
Chapter 21 Electrical Characteristics
Conditions
Min.
7.5
2.5
2.5
0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
4.0
0.5
1.0
1.0
t
VAL_*
outputs valid
HO_*
Max.
Unit
⎯
ns
⎯
ns
⎯
ns
t
CYC_SDCLK
ns
– 5.5
6.5
ns
5.2
ns
5.2
ns
6.5
ns
5.2
ns
6.5
ns
5.2
ns
6.5
ns
5.2
ns
6.5
ns
5.2
ns
6.5
ns
5.2
ns
6.5
ns
5.2
ns
6.5
ns
5.2
ns
6.5
ns
5.2
ns
⎯
ns
⎯
ns
⎯
ns
⎯
ns
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