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SMR2—Serial Mode Register 2
Bit
7
GM
Initial value
0
Read/Write
R/W
Block Transfer Mode
0
Normal Smart Card interface mode operation
• Error signal transmission/detection and automatic data retransmission performed
• TXI interrupt generated by TEND flag
• TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode)
1
Block transfer mode operation
• Error signal transmission/detection and automatic data retransmission not performed
• TXI interrupt generated by TDRE flag
• TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode)
GSM Mode
0
Normal smart card interface mode operation
• TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit
• Clock output ON/OFF control only
1
GSM mode smart card interface mode operation
• TEND flag generation 11.0 etu after beginning of start bit
• High/low fixing control possible in addition to clock output ON/OFF control (set by SCR)
Note: etu: Elementary time unit (time for transfer of 1 bit)
6
5
BLK
PE
O/E
0
0
R/W
R/W
R/W
Parity Mode
Parity Enable
0
Parity bit addition and checking disabled
1
Parity bit addition and checking enabled
H'FF88
SCI2, Smart Card Interface 2
4
3
2
BCP1
BCP0
0
0
0
R/W
R/W
Clock Select 1 and 0
0
0
ø clock
1
ø/4 clock
1
0
ø/16 clock
1
ø/64 clock
Basic Clock Pulse
0
0
32 clock periods
1
64 clock periods
1
0
372 clock periods
1
256 clock periods
*2
0
Even parity
*3
1
Odd parity
1
0
CKS1
CKS0
0
0
R/W
R/W
*1
1055
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