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Notes: *1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
*2 The receive data prior to the overrun error is retained in RDR, and the data received
subsequently is lost. Also, subsequent serial reception cannot be continued while the
ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be
continued, either.
*3 The FER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
*4 In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit
is not checked. If a framing error occurs, the receive data is transferred to RDR but the
RDRF flag is not set. Also, subsequent serial reception cannot be continued while the
FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be
continued, either.
*5 The PER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
*6 If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not
set. Also, subsequent serial reception cannot be continued while the PER flag is set to
1. In clocked synchronous mode, serial transmission cannot be continued, either.
*7 Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor
format.
*8 RDR and the RDRF flag are not affected and retain their previous values when an error
is detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
*9 Only 0 can be written, to clear the flag.
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