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RESET SEQUENCE
1. While HALT is high, RESET goes low for at least eight cycles of Ø l , Ø 2
during which all internal registers are cleared and interrupt bit (I) in
CC is set.
2. Data at FFFE loads into PCH.
3. Data at FFFF loads into PCL.
4. PC contents go out on ADRS bus during Ø l .
5. Contents of cell addressed enters instruction register during and is
decoded as first instruction.
6. If two or more byte instruction, additional bytes enter MPU for execution.
If not, go to next step.
7. After execution, step 5 is repeated for subsequent instructions.
MPU-16
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