Word Alignment - Fujitsu MB91F109 FR30 Hardware Manual

2.5

Word Alignment

Since instructions and data are accessed in bytes, mapping addresses vary depending
on instruction length or data width.
Program Access
A program running in the FR series must be placed at an address consisting of a multiple of
two.
Bit 0 of the program counter (PC) is set to 0 when the PC is updated according to instruction
execution. Bit 0 may be set to 1 only when an odd-numbered address is specified for the
branch destination address. Even at this event, bit 0 is invalid and an instruction must be
placed at an address consisting of a multiple of two.
No odd-numbered address exception occurs.
Data Access
When data access is made in the FR series, address alignment is performed forcibly in
accordance with access width as follows:
• Word access: Addresses are aligned in multiples of four (the two least significant bits are
forcibly set to 00).
• Half-word access: Addresses are aligned in multiples of two (on least significant bit is
forcibly set to 0).
• Byte access: -
As explained above, some bits are forcibly set to 0 when a word or half-word data access is
made, but this is applicable only to the calculation result of an effective address. For instance,
in @(R13, Ri) addressing mode, the register before addition is used as is for calculation (even if
the least significant bit is 1), and the least significant bit of the result of addition is masked.
Thus, the register before calculation is not masked.
[Example] LD @(R13, R2), R0
R13
00002222
R2
00000003
Result of addition
00002225
Address pin
00002224
H
H
H
Forced masking of two LSBs
H
2.5 Word Alignment
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