Interrupt Control - Renesas M16C/62P Series Hardware Manual

M16C/62P Group (M16C/62P, M16C/62PT)
12.5

Interrupt Control

The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order
they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IPL, and ILVL2 to ILVL0 bits in the each interrupt control register to enable/
disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in the each interrupt
control register.
Figure 12.3 and Figure 12.4 show the Interrupt Control Registers.
Interrupt Control Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1. This bit can only be reset by w riting "0" (Do not w rite "1").
2. To rew rite the interrupt control registers, do so at a point that does not generate the interrupt request for that register.
For details, refer to 24.6 Interrupt.
3. Use the IFSR2A register to select.
Figure 12.3 Interrupt Control Registers (1)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
(2)
Symbol
TB5IC
(3)
TB4IC/U1BCNIC
(3)
TB3IC/U0BCNIC
BCNIC
DM0IC, DM1IC
KUPIC
ADIC
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC to TA4IC
TB0IC to TB2IC
Bit Symbol
Interrupt Priority Level Select Bit
ILVL0
ILVL1
ILVL2
Interrupt Request Bit
IR
— Nothing is assigned. When w rite, set to "0".
(b7-b4) When read, their contents are indeterminate.
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Address
0045h
0046h
0047h
004Ah
004Bh, 004Ch
004Dh
004Eh
0051h, 0053h, 004Fh
0052h, 0054h, 0050h
0055h to 0059h
005Ah to 005Ch
Bit Name
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Interrupt not requested
1 : Interrupt requested
12. Interrupt
After Reset
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
Function RW
RW
RW
RW
RW
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(1)
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