Renesas M16C/62P Series Hardware Manual page 148

M16C/62P Group (M16C/62P, M16C/62PT)
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
BCLK
Address
bus
RD signal
WR signal
Data bus
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
transfer unit is 16 bits and an 8-bit bus is used
BCLK
Address
CPU use
bus
RD signal
WR signal
Data bus
(3) When the source read cycle under condition (1) has one wait state inserted
BCLK
Address
CPU use
bus
RD signal
WR signal
Data bus
(4) When the source read cycle under condition (2) has one wait state inserted
BCLK
Address
CPU use
bus
RD signal
WR signal
Data bus
NOTES :
1. The same timing changes occur with the respective conditions at the destination as at the source.
Figure 14.6 Transfer Cycles for Source Read
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
CPU use Source Destination
CPU use Source
Source Source + 1
CPU use
Source
Source
CPU use Source
Source
CPU use Source
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Dummy
cycle
Dummy
Destination
cycle
Dummy
Destination
cycle
Source + 1
Destination
Dummy
Destination
cycle
Destination
Source + 1
Source + 1
CPU use
CPU use
CPU use
Dummy
CPU use
cycle
CPU use
Dummy
CPU use
cycle
Dummy
Destination CPU use
cycle
Dummy
Destination
cycle
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14. DMAC
CPU use