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M16C/62P Group (M16C/62P, M16C/62PT)
Figure 9.6 shows the External Memory Connect Example in 4-Mbyte Mode.
In this example, the CS pin of 4-Mbyte ROM is connected to the CS0 pin of microcomputer. The 4 Mbyte ROM
address input AD21, AD20 and AD19 pins are connected to the CS3, CS2 and CS1 pins of microcomputer,
respectively. The address input AD18 pin is connected to the A19 pin of microcomputer. Figures Figure 9.7 to 9.9
show the Relationship of Addresses Between the 4-Mbyte ROM and the Microcomputer for the Case of a
Connection Example in Figure 9.6.
In microprocessor mode, or in memory expansion mode where the PM13 bit in the PM1 register is "0", banks are
located every 512 Kbytes. Setting the OFS bit in the DBR register to "1" (offset) allows the accessed address to be
offset by 40000h, so that even the data overlapping a bank boundary can be accessed in succession.
In memory expansion mode where the PM13 bit is "1," each 512-Kbyte bank can be accessed in 256 Kbyte units
by switching them over with the OFS bit.
Because the SRAM can be accessed on condition that the chip select signals S2 = H and S1 =L, CS0 and CS2 can
be connected to S2 and S1, respectively. If the SRAM does not have the input pins to accept "H" active and "L"
active chip select signals(S1, S2), CS0 and CS2 should be decoded external to the chip.
Figure 9.6
External Memory Connect Example in 4-Mbyte Mode
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
D0 to D7
A0 to A16
A17
A19
CS1
CS2
CS3
RD
CS0
WR
NOTES:
1. If only one chip select pin (S1 or S2) is present,
decoding by use of an external circuit is required.
Page 78 of 390
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9. Memory Space Expansion Function
8
DQ0 to DQ7
17
AD0 to AD16
AD17
AD18
AD19
AD20
AD21
OE
CS
DQ0 to DQ7
AD0 to AD16
OE
S2
(1)
S1
W
010-62245566 13810019655
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