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M16C/62P Group (M16C/62P, M16C/62PT)
7.2
Setting Processor Modes
Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register.
Table 7.2 shows the Processor Mode After Hardware Reset. Table 7.3 shows the PM01 to PM00 Bits Set Values
and Processor Modes.
Table 7.2
Processor Mode After Hardware Reset
CNVSS Pin Input Level
VSS
(1, 2)
VCC1
NOTES:
1. If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset 1 or
brown-out detection reset (hardware reset 2)), the internal ROM cannot be accessed regardless of
PM10 to PM00 bits.
2. The multiplexed bus cannot be assigned to the entire CS space.
Table 7.3
PM01 to PM00 Bits Set Values and Processor Modes
PM01 to PM00 Bits
00b
01b
10b
11b
Rewriting the PM01 to PM00 bits places the microcomputer in the corresponding processor mode regardless of
whether the input level on the CNVSS pin is "H" or "L". Note, however, that the PM01 to PM00 bits cannot be
rewritten to "01b" (memory expansion mode) or "11b" (microprocessor mode) at the same time the PM07 to PM02
bits are rewritten. Note also that these bits cannot be rewritten to enter microprocessor mode in the internal ROM,
nor can they be rewritten to exit microprocessor mode in areas overlapping the internal ROM.
If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset 1 or brown-out
detection reset (hardware reset 2)), the internal ROM cannot be accessed regardless of PM01 to PM00 bits.
Figures 7.1 and 7.2 show the PM0 Register and PM1 Register. Figure 7.3 show the Memory Map in Single Chip
Mode.
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Processor Modes
Single-Chip Mode
Microprocessor Mode
Processor Modes
Single-Chip Mode
Memory Expansion Mode
Do not set
Microprocessor Mode
Page 55 of 390
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7. Processor Mode
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