Renesas M16C/62P Series Hardware Manual page 210

M16C/62P Group (M16C/62P, M16C/62PT)
17.1.1.5 Serial Data Logic Switching Function
When the UiLCH bit in the UiC1 register (i = 0 to 2) = 1 (reverse), the data written to the UiTB register has its
logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the
UiRB register. Figure 17.16 shows Serial Data Logic Switching.
(1) When The UiLCH Bit in The UiC1 Register = 0 (No Reverse)
Transfer Clock
(No Reverse)
(2) When The UiLCH Bit = 1 (Reverse)
Transfer Clock
NOTES :
1. This applies to the case where the CKPOL bit in the UiC0 register = 0
i = 0 to 2
Figure 17.16 Serial Data Logic Switching
17.1.1.6 Transfer Clock Output From Multiple Pins (UART1)
Use the CLKMD1 to CLKMD0 bits in the UCON register to select one of the two transfer clock output pins
(see Figure 17.17). This function can be used when the selected transfer clock for UART1 is an internal clock.
Microcomputer
CLKS1 (P6_4)
NOTES :
1. This applies to the case where the CKDIR bit in the U1MR register= 0
Figure 17.17 Transfer Clock Output from Multiple Pins
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
"H"
"L"
"H"
TXDi
D0
"L"
"H"
"L"
"H"
TXDi
D0
(Reverse)
"L"
(transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock) and the UFORM bit = 0
(LSB first).
TXD1 (P6_7)
CLK1 (P6_5)
(internal clock) and the CLKMD1 bit in the UCON register = 1
(transfer clock output from multiple pins).
Page 195 of 390
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D1 D2 D3 D4 D5
D1 D2 D3 D4 D5
IN
CLK
Transfer enabled
when the CLKMD0
bit in the UCON
register = 0
17. Serial Interface
D6 D7
D6 D7
IN
CLK
Transfer enabled
when the CLKMD0
bit = 1
010-62245566 13810019655