Table of Contents
Advertisement
M16C/62P Group (M16C/62P, M16C/62PT)
System Clock Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1.
Rew rite this register after setting the PRC0 bit in the PRCR register to "1" (w rite enable).
2.
The CM03 bit is set to "1" (high) w hile the CM04 bit is set to "0" (I/O port) or w hen entering stop mode.
3.
This bit is provided to stop the main clock w hen the low pow er consumption mode or on-chip oscillator low pow er
dissipation mode is selected. This bit cannot be used for detection as to w hether the main clock stops or not. To
stop the main clock, set bits as follow s:
(a) Set the CM07 bit to "1" (sub clock selected) or the CM21 bit in the CM2 register to "1" (On-chip oscillator
selected)
w ith the sub-clock stably oscillates.
(b) Set the CM20 bit in the CM2 register to "0" (Oscillation stop, re-oscillation detection function disabled).
(c) Set the CM05 bit to "1" (Stop).
4.
During external clock input, Set the CM05 bit to "0" (oscillate).
5.
When CM05 bit is set to "1", the XOUT pin is held "H". Because the internal feedback resistor remains connected, the
XIN pin is pulled "H" to the same level as XOUT via the feedback resistor.
After setting the CM04 bit to "1" (XCIN-XCOUT oscillator function), w ait until the sub-clock oscillates stably before
6.
sw itching the CM07 bit from "0" to "1" (sub-clock).
7.
When entering stop mode from high-speed or middle-speed mode, on-chip oscillator mode or on-chip oscillator low
pow er mode, the CM06 bit is set to "1" (divide-by-8 mode).
8.
The fC32 clock does not stop. In low -speed mode or low pow er consumption mode, do not set this bit to "1"
(peripheral clock stops in w ait mode).
9.
To use a sub-clock, set this bit to "1". Also make sure ports P8_6 and P8_7 are directed for input, w ith no pull-ups.
10.
When the PM21 bit in the PM2 register is set to "1" (disable clock modification), this bit remains unchanged even if
w riting to the CM02, CM05, and CM07 bits.
11.
When setting the PM21 bit to "1", set the CM07 bit to "0" (main clock) before setting the PM21 bit to "1".
12.
To use the main clock as the clock source for the CPU clock, set bits as follow s.
(a) Set the CM05 bit to "0" (oscillate).
(b) Wait the main clock oscillation stabilizes.
(c) Set the CM11, CM21 and CM07 bits to "0".
13.
When the CM21 bit is set to "0" (on-chip oscillator stops) and the CM05 bit is set to "1" (main clock stops), the CM06
bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capacity High).
14.
To return from on-chip oscillator mode to high-speed or middle-speed mode, set the CM06 and CM15 bits to "1".
Figure 10.2
CM0 Register
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
(1)
Symbol
Address
0006h
CM0
Bit Symbol
Bit Name
Clock Output Function
CM00
Select Bit
(Valid only in single-chip
mode)
CM01
WAIT Mode Peripheral
Function Clock Stop Bit
CM02
XCIN-XCOUT Drive
CM03
Capacity Select Bit
Port XC Select Bit
CM04
Main Clock Stop Bit
CM05
(3, 10, 12, 13)
Main Clock Division
CM06
(7, 13, 14)
Select Bit 0
System Clock Select Bit
CM07
(6, 10, 11, 12)
Page 84 of 390
提供单片机解密、IC解密、芯片解密业务
b1 b0
0 0 : I/O port P5_7
0 1 : Output fC
1 0 : Output f8
1 1 : Output f32
0 : Peripheral function clock does not stop in
(10)
w ait mode
1 : Peripheral function clock stops in w ait
(8)
mode
0 : LOW
(2)
1 : HIGH
(2)
0 : I/O ports P8_6, P8_7
1 : XCIN-XCOUT oscillation function
0 : On
(4, 5)
1 : Off
0 : CM16 and CM17 enabled
1 : Division-by-8 mode
0 : Main clock, PLL clock, or on-chip oscillator clock
1 : Sub clock
10. Clock Generation Circuit
After Reset
01001000b
Function
(9)
010-62245566 13810019655
RW
RW
RW
RW
RW
RW
RW
RW
RW
Advertisement
Table of Contents
