Renesas M16C/62P Series Hardware Manual page 71

M16C/62P Group (M16C/62P, M16C/62PT)
Processor Mode Register 0
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (w rite enable).
2. Effective w hen the PM01 to PM00 bits are set to "01b" (memory expansion mode) or "11b" (microprocessor mode).
3. To set the PM01 to PM00 bits are "01b" and the PM05 to PM04 bits are "11b" (multiplexed bus assigned to the entire
___
CS space), apply an "H" signal to the BYTE pin (external data bus is 8 bits w ide). While the CNVSS pin is held "H"
(= VCC1), do not rew rite the PM05 to PM04 bits to "11b" after reset.
If the PM05 to PM04 bits are set to "11b" during memory expansion mode, P3_1 to P3_7 and P4_0 to P4_3 become
I/O ports, in w hich case the accessible area for each CS
4. The PM01 to PM00 bits do not change at softw are reset, w atchdog timer reset and oscillation stop detection reset.
Figure 7.1 PM0 Register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
(1)
Symbol Address
0004h
PM0
Bit Symbol Bit Name
Processor Mode Bit
PM00
PM01
R/W Mode Select Bit
PM02
Softw are Reset Bit
PM03
Multiplexed Bus Space Select
(2)
Bit
PM04
PM05
Port P4_0 to P4_3 Function
PM06
(2)
Select Bit
BCLK Output Disable Bit
PM07
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00000000b (CNVSS pin = L)
00000011b (CNVSS pin = H)
(4)
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Do not set
1 1 : Microprocessor mode
___ _____ ____
(2)
0 : RD , BHE , WR
___ ______ _____
1 : RD , WRH , WRL
Setting this bit to "1" resets the microcomputer.
When read, its content is "0".
b5 b4
0 0 : Multiplexed bus is unused
(Separate bus in the entire CS
_____
0 1 : Allocated to CS2
_____
1 0 : Allocated to CS1
1 1 : Allocated to the entire CS
0 : Address output
1 : Port function (Address is not output)
(2) 0 : BCLK is output
1 : BCLK is not output (Pin is left high-impedance)
___
is 256 bytes.
7. Processor Mode
After Reset
Function
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space)
space
space
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(3)
space
010-62245566 13810019655
RW
RW
RW
RW
RW
RW
RW
RW
RW