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M16C/62P Group (M16C/62P, M16C/62PT)
(1) Example of Transmit Timing (when internal clock is selected)
Transfer clock
"1"
TE bit in
"0"
UiC1 register
"1"
TI bit in
UiC1 register
"0"
"H"
CTSi
"L"
CLK
i
TXDi
TXEPT bit in
"1"
UiC0 register
"0"
"1"
IR bit in
SiTIC register
"0"
i = 0 to 2
The above timing diagram applies to the case where the register bits are set as follows:
· CKDIR bit in UiMR register = 0 (internal clock)
· CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
· CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data
· UiIRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
(2) Example of Receive Timing (when external clock is selected)
"1"
RE bit in
UiC1 register
"0"
TE bit in
"1"
UiC1 register
"0"
"1"
TI bit in
UiC1 register
"0"
"H"
RTSi
"L"
CLKi
RXDi
Data is transferred from the UARTi
RI bit in
"1"
receive register to the UiRB register
UiC1 register
"0"
"1"
IR bit in
SiRIC register
"0"
OER flag in UiRB
"1"
register
"0"
i=0 to 2
The above timing diagram applies to the case where the register bits are set
as follows:
· CKDIR bit in UiMR register = 1 (external clock)
· CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
· CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive
fEXT: frequency of external clock
Figure 17.13
Transmit and Receive Operation
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Tc
Data is set in the UiTB register
Data is transferred from the UiTB register to the UARTi transmit register
T
CLK
D0 D1 D2 D3 D4 D5 D6 D7
taken in at the rising edge of the transfer clock)
Dummy data is set in the to UiTB register
Data is transferred from the UiTB register to the UARTi transmit register
1 / fEXT
Received data is taken in
D0 D1 D2 D3 D4 D5 D6 D7
Set to "0" by an interrupt request acknowledgement or by program
data taken in at the rising edge of the transfer clock)
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Pulse stops because an "H" signal is
applied to CTSi
D0 D1 D2 D3 D4 D5 D6 D7
Set to "0" by an interrupt request acknowledgement or by program
TC = TCLK = 2(n + 1) / fj
An "L" signal is applied when
the UiRB register is read
D0 D1 D2 D3 D4 D5
D6
D7
Read by the UiRB register
Make sure the following conditions are met when input to
the CLKi pin before receiving data is high:
· TE bit in UiC0 register = 1 (transmit enabled)
· RE bit in UiC0 register = 1 (receive enabled)
· Write dummy data to the UiTB register
17. Serial Interface
Pulse stops because the TE bit is set to "0"
D0 D1 D2 D3 D4 D5 D6 D7
fj: frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
n: value set to UiBRG register
D0 D1 D2 D3 D4 D5
D6
010-62245566 13810019655
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