Renesas M16C/62P Series Hardware Manual page 307

M16C/62P Group (M16C/62P, M16C/62PT)
Table 22.5 Status Register
Bits in Status Bit in FMR0
Register Register
SR0 (D0)
SR1 (D1)
SR2 (D2)
SR3 (D3)
SR4 (D4) FMR06
SR5 (D5) FMR07
SR6 (D6)
SR7 (D7) FMR00
• D0 to D7: These data buses are read when the read status register command is executed.
• The FMR07 bit (SR5) and FMR06 bit (SR4) are set to "0" by executing the clear status register
command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to "1," the program, block erase, erase all
unlocked block and lock bit program commands are not accepted.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Status name
−
Reserved
−
Reserved
−
Reserved
−
Reserved
Program status
Erase status
−
Reserved
Sequencer status
Page 292 of 390
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Definition
"0"
−
−
−
−
Terminated normally Terminated in error
Terminated normally Terminated in error
−
Busy
22. Flash Memory Version
Value after
"1" Reset
− −
− −
− −
− −
0
0
− −
Ready 1
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