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M16C/62P Group (M16C/62P, M16C/62PT)
Memory Expansion Mode, Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplex bus selection )
Read timing
BCLK
CSi
ADi
/DBi
ADi
BHE
t
d(BCLK-ALE)
ALE
RD
Write timing
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
WR,WRL,
WRH
Measuring conditions
· V
=V
=5V
CC1
CC2
· Input timing voltage : V
· Output timing voltage : V
Figure 23.10
Timing Diagram (8)
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
t
d(BCLK-CS)
25ns.max
t
d(AD-ALE)
(0.5×t
-25)ns.min
cyc
Address
t
d(BCLK-AD)
25ns.max
t
h(BCLK-ALE)
−4ns.min
25ns.max
t
t
d(BCLK-CS)
25ns.max
Address
t
d(AD-ALE)
(0.5×t
-25)ns.min
cyc
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
25ns.max
−4ns.min
=0.8V, V
=2.0V
IL
IH
=0.4V, V
=2.4V
OL
OH
Page 327 of 390
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t
cyc
t
h(ALE-AD)
(0.5×t
-15)ns.min
cyc
t
dZ(RD-AD)
8ns.max
t
ac3(RD-DB)
(1.5×t
-45)ns.max
cyc
t
d(AD-RD)
0ns.min
d(BCLK-RD)
25ns.max
t
cyc
t
d(BCLK-DB)
40ns.max
Data output
t
d(DB-WR)
(1.5×t
-40)ns.min
cyc
t
d(AD-WR)
0ns.min
t
d(BCLK-WR)
25ns.max
23. Electrical Characteristics
V
=V
CC1
CC2
t
h(BCLK-CS)
t
h(RD-CS)
4ns.min
(0.5×t
-10)ns.min
cyc
Address
Data input
t
h(RD-DB)
t
su(DB-RD)
0ns.min
40ns.min
t
h(BCLK-AD)
4ns.min
t
h(RD-AD)
(0.5×t
-10)ns.min
cyc
t
h(BCLK-RD)
0ns.min
t
t
h(BCLK-CS)
h(WR-CS)
4ns.min
(0.5×t
-10)ns.min
cyc
t
h(BCLK-DB)
4ns.min
Address
t
h(WR-DB)
(0.5×t
-10)ns.min
cyc
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5×t
-10)ns.min
cyc
t
h(BCLK-WR)
0ns.min
010-62245566 13810019655
=5V
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