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M16C/62P Group (M16C/62P, M16C/62PT)
Memory Expansion Mode, Microprocessor Mode
( for 2-wait setting and external area access )
Read timing
BCLK
CSi
ADi
BHE
t
d(BCLK-ALE)
30ns.max
ALE
RD
DBi
Write timing
BCLK
CSi
ADi
BHE
t
d(BCLK-ALE)
30ns.max
ALE
WR, WRL
WRH
DBi
1
t
=
cyc
f(BCLK)
Measuring conditions
· V
=V
=3V
CC1
CC2
· Input timing voltage : V
· Output timing voltage : V
Figure 23.18
Timing Diagram (6)
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
t
cyc
t
d(BCLK-CS)
30ns.max
t
d(BCLK-AD)
30ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
30ns.max
t
ac2(RD-DB)
(2.5 × t
-60)ns.max
cyc
Hi-Z
t
cyc
t
d(BCLK-CS)
30ns.max
t
d(BCLK-AD)
30ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-WR)
30ns.max
t
d(BCLK-DB)
40ns.max
Hi-Z
t
d(DB-WR)
(1.5 × t
-40)ns.min
cyc
=0.6V, V
=2.4V
IL
IH
=1.5V, V
=1.5V
OL
OH
Page 342 of 390
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t
h(BCLK-CS)
4ns.min
t
h(BCLK-AD)
4ns.min
t
h(RD-AD)
0ns.min
t
h(BCLK-RD)
0ns.min
t
t
su(DB-RD)
h(RD-DB)
50ns.min
0ns.min
t
h(BCLK-CS)
4ns.min
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 × t
-10)ns.min
cyc
t
h(BCLK-WR)
0ns.min
t
h(BCLK-DB)
4ns.min
t
h(WR-DB)
(0.5 × t
-10)ns.min
cyc
23. Electrical Characteristics
V
=V
=3V
CC1
CC2
010-62245566 13810019655
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