Saving Registers - Renesas M16C/62P Series Hardware Manual

M16C/62P Group (M16C/62P, M16C/62PT)
12.5.7

Saving Registers

In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register,
16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved.
Figure 12.7 shows the Stack Status Before and After Acceptance of Interrupt Request.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use the
PUSHM instruction, and all registers except SP can be saved with a single instruction.
Address
MSB
m − 4
m − 3
m − 2
m − 1
m
Content of previous stack
Content of previous stack
m + 1
Stack status before interrupt request
is acknowledged
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
PCL : 8 low-order bits of PC
Figure 12.7 Stack Status Before and After Acceptance of Interrupt Request
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Stack
LSB
[SP]
SP value before
interrupt request is
accepted.
FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
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Stack
Address
MSB
m − 4
PCL
m − 3
PCM
m − 2
FLGL
m − 1
FLGH PCH
m
Content of previous stack
Content of previous stack
m + 1
Stack status after interrupt request
is acknowledged
12. Interrupt
LSB
[SP]
New SP value
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