Renesas M16C/62P Series Hardware Manual page 240

M16C/62P Group (M16C/62P, M16C/62PT)
Figure 17.35 SIM Interface Connection
17.1.6.1 Parity Error Signal Output
The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to "1".
The parity error signal is output when a parity error is detected while receiving data. This is achieved by pulling
the TXD2 output low with the timing shown in Figure 17.36. If the R2RB register is read while outputting a
parity error signal, the PER bit is cleared to "0" and at the same time the TXD2 output is returned high.
When transmitting, a transmission-finished interrupt request is generated at the falling edge of the transfer clock
pulse that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be
determined by reading the port that shares the RXD2 pin in a transmission-finished interrupt routine.
Transfer
clock
RXD2
TXD2
IR bit in U2C1
register
This timing diagram applies to the case where the direct format is
implemented.
NOTES :
1. The output of microcomputer is in the high-impedance state
(pulled up externally).
Figure 17.36 Parity Error Signal Output Timing
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Microcomputer
TXD2
RXD2
"H"
"L"
"H"
ST D0 D1
"L"
"H"
"L"
"1"
"0"
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SIM card
D2 D3 D4 D5 D6
(NOTE 1)
17. Serial Interface
D7 P SP
ST : Start bit
P : Even Parity
SP : Stop bit
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