Renesas M16C/62P Series Hardware Manual page 132

M16C/62P Group (M16C/62P, M16C/62PT)
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP
time of acceptance of an interrupt request, is even or odd. If the stack pointer
the PC are saved,16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 12.8 shows the
Operation of Saving Register.
NOTES:
1.When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated by the
U flag. Otherwise, it is the ISP.
(1) SP contains even number
[SP] − 5 (Odd)
[SP] − 4 (Even)
[SP] − 3(Odd)
[SP] − 2 (Even)
[SP] − 1(Odd)
[SP]
(2) SP contains odd number
[SP] − 5 (Even)
[SP] − 4(Odd)
[SP] − 3 (Even)
[SP] − 2(Odd)
[SP] − 1 (Even)
[SP]
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
PCL
NOTES :
Figure 12.8 Operation of Saving Register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Address Stack
PCL
PCM
FLGL
FLGH
(Even)
Address Stack
PCL
PCM
FLGL
FLGH
(Odd)
: 8 low-order bits of PC
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
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Sequence in which order
registers are saved
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
PCH
Finished saving registers
in two operations.
Sequence in which order
registers are saved
(3)
(4)
Saved, 8 bits at a time
(1)
PCH
(2)
Finished saving registers
in four operations.
FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
12. Interrupt
(1)
, at the
(1)
is even, the FLG register and
010-62245566 13810019655