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M16C/62P Group (M16C/62P, M16C/62PT)
Table 10.8
Allowed Transition and Setting
Current
High-Speed Mode,
State
Middle-Speed Mode
Low-Speed Mode
Low Power
Dissipation Mode
PLL Operating
(2)
Mode
On-chip Oscillator
Mode
On-chip Oscillator
Low Power
Dissipation Mode
Stop Mode
Wait Mode
NOTES:
1.
Avoid making a transition when the CM20 bit is set in to "1" (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to "0" (oscillation stop, re-oscillation detection function disabled) before transiting.
2.
On-chip oscillator clock oscillates and stops in low-speed mode. In this mode, the on-chip oscillator can be used as peripheral function clock.
Sub clock oscillates and stops in PLL operating mode. In this mode, sub clock can be used as peripheral function clock.
3.
PLL operating mode can only be entered from and changed to high-speed mode.
4.
Set the CM06 bit to "1" (division by 8 mode) before transiting from on-chip oscillator mode to high- or middle-speed mode.
5.
When exiting stop mode, the CM0S6 bit is set to "1" (division by 8 mode).
6.
If the CM05 bit set to "1" (main clock stop), then the CM06 bit is set to "1" (division by 8 mode).
7.
A transition can be made only when sub clock is oscillating.
8.
State transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in the table below.
No
Division
No Division
Divided by 2
Divided by 4
Divided by 8
Divided by 16
No Division
Divided by 2
Divided by 4
Divided by 8
Divided by 16
9.
( ) : setting method. See the following table.
Setting
(1)
CM04 = 0
(2)
CM04 = 1
(3)
CM06 = 0, CM17 = 0, CM16 = 0
(4)
CM06 = 0, CM17 = 0, CM16 = 1
(5)
CM06 = 0, CM17 = 1, CM16 = 0
(6)
CM06 = 0, CM17 = 1, CM16 = 1
(7)
CM06 = 1
(8)
CM07 = 0
(9)
CM07 = 1
CM04, CM05, CM06, CM07
CM10, CM11, CM16, CM17
CM20, CM21
PLC07
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
High-Speed Mode,
Low-Speed
(2)
Middle-Speed
Mode
Mode
(NOTE 7)
(NOTE 8)
(9)
(2)
(8)
−
(10)
−
(NOTE 3)
(12)
−
(NOTE 4)
(14)
−
−
(NOTE 5)
(18)
(18)
(18)
(18)
Sub Clock Oscillating
Divided by
Divided by
2
4
(4)
(5)
(3)
(5)
(3)
(4)
(3)
(4)
(5)
(3)
(4)
(5)
−
−
(2)
−
−
(2)
−
−
(2)
−
−
−
−
−
−
Operation
Sub clock turned off
Sub clock oscillating
CPU clock no division mode
CPU clock division by 2 mode
CPU clock division by 4 mode
CPU clock division by 16 mode
CPU clock division by 8 mode
Main clock, PLL clock, or on-chip
oscillator clock selected
Sub clock selected
: Bits in CM0 register
: Bits in CM1 register
: Bits in CM2 register
: Bits in PLC0 register
Page 101 of 390
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(9)
State After Transition
Low Power
PLL
Dissipation
Operating
(2)
Mode
Mode
(13)
-
(NOTE 3)
(11)
−
(NOTE 1, 6)
−
−
−
−
−
−
−
(18)
−
(18)
Divided by
Divided by
No
8
16
Division
(7)
(6)
(1)
−
(7)
(6)
−
(7)
(6)
−
(6)
−
(7)
−
−
−
−
(3)
−
−
(3)
−
(2)
(3)
−
(2)
(3)
Setting
(10)
CM05 = 0
(11)
CM05 = 1
(12)
PLC07=0, CM11=0
(13)
PLC07=1, CM11=1
(14)
CM21=0
(15)
CM21=1
(16)
CM10=1
(17)
Wait Instruction
(18)
Hardware Interrupt
10. Clock Generation Circuit
On-chip
On-chip Oscillator
Oscillator
Low Power
Mode
Dissipation Mode
−
(15)
−
−
−
−
−
−
(NOTE 1)
(NOTE 8)
(11)
(10)
(NOTE 8)
(18)
(NOTE 5)
(18)
(NOTE 5)
(18)
(18)
Sub Clock Turned Off
Divided by
Divided by
Divided by
2
4
8
−
−
−
−
−
(1)
−
−
(1)
−
−
(1)
−
−
−
(4)
(5)
(7)
(5)
(7)
(4)
(7)
(4)
(5)
(4)
(5)
(7)
Operation
Main clock oscillating
Main clock turned off
Main clock selected
PLL clock selected
Main clock or PLL clock selected
On-chip oscillator clock selected
Transition to stop mode
Transition to wait mode
Exit stop mode or wait mode
010-62245566 13810019655
Stop
Wait
Mode
Mode
(16)
(17)
(NOTE 1)
(16)
(17)
(NOTE 1)
(16)
(17)
(NOTE 1)
−
−
(16)
(17)
(NOTE 1)
(16)
(17)
(NOTE 1)
−
−
− : Cannot transit
Divided by
16
−
−
−
−
(1)
(6)
(6)
(6)
(6)
− : Cannot transit
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