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M16C/62P Group (M16C/62P, M16C/62PT)
UART Transmit/Receive Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1. When using multiple transfer clock output pins, make sure the follow ing conditions are met:
CKDIR bit in the U1MR register = 0 (internal clock)
UARTi Special Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1.
The BBS bit is set to "0" by w riting "0" in a program (Writing "1" has no ef f ect).
2.
Underf low signal of Timer A 3 in UA RT0, underf low signal of Timer A 4 in UA RT1, underf low signal of Timer A 0 in
UA RT2.
3.
When a transf er begins, the SSS bit is set to "0" (Not synchronized to RXDi).
4.
The f unction of the bit 3 varies depending on the product.
If the product is M3062LFGPFP or M3062LFGPGP, the bit 3 becomes the LSY N bit.
If the product is other than M3062LFGPFP and M3062LFGPGP, the bit 3 is reserved. Theref ore, set it to 0.
(The LSY N bit is an SCLL sync output enable bit.)
When the LSY N bit is set to "1" and the SCLi pin outputs an "L" level signal, the data bit, such as the P6_2 bit in the P6
register f or SCL0 pin, the P6_6 bit in the P6 register f or SCL1 pin, and the P7_1 bit in the P7 register f or SCL2 pin, is set
to "1".
Figure 17.10
UCON and UiSMR Registers
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Symbol
Address
03B0h
UCON
Bit Symbol
Bit Name
UART0 Transmit Interrupt Factor
U0IRS
Select Bit
UART1 Transmit Interrupt Factor
U1IRS
Select Bit
UART0 Continuous Receive
U0RRM
Mode Enable Bit
UART1 Continuous Receive
U1RRM
Mode Enable Bit
UART1 CLK/CLKS Select Bit 0
CLKMD0
UART1 CLK/CLKS Select Bit 1
CLKMD1
Separate UART0
______
_____
CTS/
RTS
Bit
RCSP
—
Nothing is assigned. When w rite, set to "0".
(b7)
When read, its content is indeterminate.
Symbol
036Fh, 0373h, 0377h
U0SMR to U2SMR
Bit Name
Bit Symbol
2
I
C Mode Select Bit
IICM
A rbitration Lost Detecting Flag
A BC
Control Bit
Bus Busy Flag
BBS
—
Reserved Bit
(b3)
(4)
SCLL sync output enable bit
(4)
LSY N
Bus Collision Detect Sampling
A BSCS
Clock Select Bit
A uto Clear Function Select Bit
A CSE
of Transmit Enable Bit
Transmit Start Condition Select
SSS
Bit
—
Nothing is assigned.
(b7)
When w rite, set to "0". When read, its content is indeterminate.
Page 186 of 390
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After Reset
X0000000b
Function
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Continuous receive mode disabled
1 : Continuous receive mode enable
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
Effective w hen CLKMD1 = 1
0 : Clock output from CLK1
1 : Clock output from CLKS1
(1)
0 : CLK output is only CLK1
1 : Transfer clock output from multiple pins
function selected
_____
_____
0 : CTS/
RTS
shared pin
_____
_____
1 : CTS
/RTS
separated
(CTS0 supplied from the P6_4 pin)
A ddress
Function
2
0 : Other than I
C mode
2
1 : I
C mode
0 : Update per bit
1 : Update per byte
0 : STOP condition detected
1 : STA RT condition detected (busy)
Set to "0"
0 : Disable
1 : Enable
0 : Rising edge of transf er clock
1 : Underf low signal of Timer A j
0 : No auto clear f unction
1 : A uto clear at occurrence of bus collision
0 : Not synchronized to RXDi
1 : Synchronized to RXDi
17. Serial Interface
RW
RW
RW
RW
RW
RW
RW
RW
—
A f ter Reset
X0000000b
RW
RW
RW
(1)
RW
RW
RW
(2)
RW
RW
(3)
—
010-62245566 13810019655
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