Renesas M16C/62P Series Hardware Manual page 103

M16C/62P Group (M16C/62P, M16C/62PT)
PLL Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0 0 1
NOTES :
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (w rite enable).
2. When the PM21 bit in the PM2 register is "1" (clock modification disable), w riting to this register has no effect.
3. These three bits can only be modified w hen the PLC07 bit = 0 (PLL turned off). The value once w ritten to this bit
cannot be modified.
4. Before setting this bit to "1", set the CM07 bit in the CM0 register to "0" (main clock), set the CM17 to CM16 bits in the
CM1 register to "00b" (main clock undivided mode), and set the CM06 bit in the CM0 register to "0" (CM16 and CM17
bits enable).
Figure 10.6 PLC0 Register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
(1, 2)
Symbol Address
001Ch
PLC0
Bit Symbol Bit Name
PLL Multiplying Factor
(3)
Select Bit
PLC00
PLC01
PLC02
— Nothing is assigned. When w rite, set to "0".
(b3) When read, its content is indeterminate.
— Reserved Bit
(b4)
— Reserved Bit
(b6-b5)
Operation Enable Bit
PLC07
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b2 b1 b0
0 0 0 : Do not set
0 0 1 : Multiply by 2
0 1 0 : Multiply by 4
0 1 1 : Multiply by 6
1 0 0 : Multiply by 8
1 0 1 :
1 1 0 : Do not set
1 1 1 :
Set to "1"
Set to "0"
(4)
0: PLL Off
1: PLL On
10. Clock Generation Circuit
After Reset
0001X010b
Function
010-62245566 13810019655
RW
RW
RW
RW
—
RW
RW
RW