Event Counter Mode - Renesas M16C/62P Series Hardware Manual

M16C/62P Group (M16C/62P, M16C/62PT)
15.2.2

Event Counter Mode

In event counter mode, the timer counts pulses from an external device or overflows and underflows of other
timers (see Table 15.7). Figure 15.20 shows TBiMR Register in Event Counter Mode.
Table 15.7 Specifications in Event Counter Mode
Item
Count Source
Count Operation
Divide Ratio
Count Start Condition
Count Stop Condition
Interrupt Request
Generation Timing
TBiIN Pin Function
Read from Timer
Write to Timer
NOTES:
1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to
TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
• External signals input to TBiIN pin (i=0 to 5) (effective edge can be selected in
program)
• Timer Bj overflow or underflow (j=i-1, except j=2 if i=0, j=5 if i=3)
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
1/(n+1) n: set value of TBi register
(1)
Set TBiS bit to "1" (= start counting)
Set TBiS bit to "0" (= stop counting)
Timer underflow
Count source input
Count value can be read by reading TBi register
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
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Specification
0000h to FFFFh
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15. Timers