Renesas M16C/62P Series Hardware Manual page 185

M16C/62P Group (M16C/62P, M16C/62PT)
Timer B2 Special Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (w rite enable).
2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (saw tooth w ave modulation mode), set this bit to "0" (Timer
B2 underflow ).
3. Related pins are U(P8_0/TA4OUT), U
W(P7_4/TA2OUT), W
pin w hen the IVPCR1 bit = 1, the target pins go to a high-impedance state regardless of w hich functions of those pins are
being used. After forced interrupt (cutoff), input "H" to the NMI
Three-Phase Output Buffer Register i
b7 b6 b5 b4 b3 b2 b1 b0
0 0
NOTES :
1. Values of the IDB0 and IDB1 registers are transferred to the three-phase output shift register by a transfer trigger.
After the transfer trigger occurs, the values w ritten in the IDB0 register determine each phase output signal first.
Then the value w ritten in the IDB1 register on the falling edge of Timers A1, A2 and A4 one-shot pulse determines
each phase output signal.
Figure 16.5 TB2SC, IDB0 and IDB1 Registers
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
(1)
Symbol Address
TB2SC
Bit Name
Bit Symbol
Timer B2 Reload Timing
Sw itching Bit
PWCOM
Three Phase Output Port NMI
Control Bit 1(3)
IVPCR1
— Nothing is assigned. When w rite, set to "0".
(b7-b2) When read, their contents are indeterminate.
__
(P8_1/TA4IN), V(P7_2/CLK2/TA1OUT), V
___
(P7_5/TA2IN). If a low -level signal is applied to the NMI
(1)
(i=0, 1)
Symbol Address
034Ah, 034Bh
IDB0, IDB1
Bit Symbol Bit Name
U-Phase Output Buffer i
DUi
__
U -Phase Output Buffer i
DUBi
V-Phase Output Buffer i
DVi
__
V -Phase Output Buffer i
DVBi
W-Phase Output Buffer i
DWi
__
W -Phase Output Buffer i
DWBi
— Reserved Bit
(b7-b6)
Page 170 of 390
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16. Three-Phase Motor Control Timer Function
039Eh
0 : Timer B2 underflow
1 : Timer A output at odd-numbered
occurrences
____
0 : Three-phase output forcible cutoff by NMI
input (high-impedance) disabled
1 : Three-phase output forcible cutoff by NMI
input (high-impedance) enabled
__
(P7_3/CTS2/RTS2/TA1IN),
____
____
pin and set IVPCR1 bit to "0": this forced cutoff w ill be reset.
Write output level
0 : Active level
1 : Inactive level
When read, the value of the three-phase shift
register is read.
Set to "0"
After Reset
XXXXXX00b
Function
(2)
____
____
After Reset
00h
Function
010-62245566 13810019655
RW
RW
RW
—
RW
RW
RW
RW
RW
RW
RW
RO