Software Wait - Renesas M16C/62P Series Hardware Manual

M16C/62P Group (M16C/62P, M16C/62PT)
8.2.10

Software Wait

Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits in the
CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is always
accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. See Table 8.8 Bit
and Bus Cycle Related to Software Wait for details.
To use the RDY signal, set the corresponding CS3W to CS0W bit to "0" (with wait state). Figure 8.6 shows the
CSE Register. Table 8.8 shows the Bit and Bus Cycle Related to Software Wait. Figure 8.7 and 8.8 show the
Typical Bus Timings Using Software Wait.
Chip Select Expansion Control Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1. Set the CSiW bit (i = 0 to 3) in the CSR register to "0" (w ith w ait state) before w riting to the CSEi1W to CSEi0W bits.
If the CSiW bit needs to be set to "1" (w ithout w ait state), set the CSEi1W to CSEi0W bits to "00b" before setting it.
Figure 8.6 CSE Register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Symbol
CSE
Bit Name
Bit Symbol
_____
CS0 Wait Expansion Bit
CSE00W
CSE01W
_____
CS1 Wait Expansion Bit
CSE10W
CSE11W
_____
CS2 Wait Expansion Bit
CSE20W
CSE21W
_____
CS3 Wait Expansion Bit
CSE30W
CSE31W
Page 68 of 390
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Address
001Bh
(1)
b1 b0
0 0 : 1 w ait
0 1 : 2 w aits
1 0 : 3 w aits
1 1 : Do not set
(1)
b3 b2
0 0 : 1 w ait
0 1 : 2 w aits
1 0 : 3 w aits
1 1 : Do not set
(1)
b5 b4
0 0 : 1 w ait
0 1 : 2 w aits
1 0 : 3 w aits
1 1 : Do not set
(1)
b7 b6
0 0 : 1 w ait
0 1 : 2 w aits
1 0 : 3 w aits
1 1 : Do not set
After Reset
00h
Function
010-62245566 13810019655
8. Bus
RW
RW
RW
RW
RW
RW
RW
RW
RW