Renesas M16C/62P Series Hardware Manual page 359

M16C/62P Group (M16C/62P, M16C/62PT)
Memory Expansion Mode, Microprocessor Mode
(For 2-wait setting, external area access and multiplex bus selection)
Read timing
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
RD
Write timing
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
WR,WRL,
WRH
1
t =
cyc
f(BCLK)
Measuring conditions
· V =V =3V
CC1 CC2
· Input timing voltage : V
· Output timing voltage : V
Figure 23.20 Timing Diagram (8)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
t
d(BCLK-CS)
40ns.max
t
d(AD-ALE)
(0.5 × t
-40)ns.min
cyc
Address
t
d(BCLK-AD)
40ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
40ns.max
-4ns.min
t
t
d(BCLK-CS)
40ns.max
Address
t
d(AD-ALE)
(0.5 × t
-40)ns.min
cyc
t
d(BCLK-AD)
40ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
40ns.max
-4ns.min
=0.6V, V =2.4V
IL IH
=1.5V, V =1.5V
OL OH
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t
cyc
t
h(ALE-AD)
(0.5 × t
-15)ns.min
cyc
t
dZ(RD-AD)
8ns.max
t
ac3(RD-DB)
(1.5 × t
-60)ns.max
cyc
t
d(AD-RD)
0ns.min
d(BCLK-RD)
40ns.max
t
cyc
t
d(BCLK-DB)
50ns.max
Data output
t
d(DB-WR)
(1.5 × t
-50)ns.min
cyc
t
d(AD-WR)
0ns.min
t
d(BCLK-WR)
40ns.max
23. Electrical Characteristics
V =V =3V
CC1 CC2
t
h(BCLK-CS)
t
h(RD-CS)
4ns.min
(0.5 × t
-10)ns.min
cyc
Address
Data input
t
h(RD-DB)
t
su(DB-RD)
0ns.min
50ns.min
t
h(BCLK-AD)
4ns.min
t
h(RD-AD)
(0.5 × t
-10)ns.min
cyc
t
h(BCLK-RD)
0ns.min
t
t h(BCLK-CS)
h(WR-CS)
4ns.min
(0.5 × t
-10)ns.min
cyc
t
h(BCLK-DB)
4ns.min
Address
t
h(WR-DB)
(0.5 × t
-10)ns.min
cyc
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 × t
-10)ns.min
cyc
t
h(BCLK-WR)
0ns.min
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