Renesas M16C/62P Series Hardware Manual page 208

M16C/62P Group (M16C/62P, M16C/62PT)
17.1.1.1 Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow
the procedures below.
•
Resetting the UiRB register (i=0 to 2)
(1) Set the RE bit in the UiC1 register to "0" (reception disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to "000b" (Serial interface disabled)
(3) Set the SMD2 to SMD0 bits in the UiMR register to "001b" (Clock synchronous serial I/O mode)
(4) Set the RE bit in the UiC1 register to "1" (reception enabled)
•
Resetting the UiTB register (i=0 to 2)
(1) Set the SMD2 to SMD0 bits in the UiMR register "000b" (Serial interface disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register "001b" (Clock synchronous serial I/O mode)
(3) "1" is written to RE bit in the UiC1 register (transmission enabled), regardless of the TE bit in the UiCi
register
17.1.1.2 CLK Polarity Select Function
Use the CKPOL bit in the UiC0 register (i = 0 to 2) to select the transfer clock polarity. Figure 17.14 shows the
Transfer Clock Polarity.
(1) When the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
CLKi
TXDi
RXDi
(2) When the CKPOL bit = 1 (transmit data output at the rising edge and the receive
data taken in at the falling edge of the transfer clock)
CLKi
TXDi
RXDi
NOTES:
1. This applies to the case where the UFORM bit in the UiC0 register = 0
(LSB first) and the UiLCH bit in the UiC1 register = 0 (no reverse).
2. When not transferring, the CLKi pin outputs a high signal.
3. When not transferring, the CLKi pin outputs a low signal.
i = 0 to 2
Figure 17.14 Transfer Clock Polarity
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
Page 193 of 390
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D4 D5 D6 D7
D4 D5 D6 D7
D4 D5 D6 D7
D4 D5 D6 D7
17. Serial Interface
(NOTE 2)
(NOTE 3)
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